Texas Instruments ADS1285EVM-PDK, Руководство пользователя, Страница: 9 / 40

4 Digital Interface
As noted in Section 1 , the EVM interfaces with the PHI and communicates with the computer over the USB.
There are two devices on the EVM with which the PHI communicates: the ADS1285 ADC (over SPI) and the
EEPROM (over I
2
C). The EEPROM comes pre-programmed with the information required to configure and
initialize the ADS1285EVM-PDK GUI. When the hardware is initialized, the EEPROM is no longer used.
4.1 Connection to the PHI
The ADS1285EVM-PDK board communicates with the PHI through a shrouded, 60-pin connector, J6. There are
two round standoffs next to J6 with Phillips-head screws. To connect the PHI to the EVM, remove the screws,
attach the PHI to the EVM, and replace the screws into the standoffs. The screws secure the EVM to the PHI
and ensures the connection between the boards.
Table 4-1 lists the different PHI connection and their functions.
Table 4-1. PHI Connector Pin Functions
PHI Connector Pin Name PHI Connector Pin Function
5.5V J6[1] Power-supply source for the analog section of the EVM
GND J6[3] Ground
~RESET J6[6] ADC reset pin, active low
~PWDN J6[8] ADC power-down pin, active low
SYNC J6[12] ADC synchronization, active high
DIN_PHI J6[12]
SPI: DIN from the ADC, POCI, or serial interface data in (pre-RTM
GUI revision compatibility)
GPIO1 J6[14] General-purpose I/O 1 pin from the ADC
GPIO0 J6[16] General-purpose I/O 0 pin from the ADC
DIN_PHI J6[18]
SPI: DIN from the ADC, POCI, or serial interface data in (RTM GUI
revision compatibility)
~CS_ADC J6[22] SPI: CS, chip-select, or serial interface select, active low for the ADC
SCLK_PHI J6[24] SPI: Serial interface clock, or SCLK
CAPCLK_OUT J6[26]
Output path for the PHI signal to synchronize captures with any delay
from the EVM
CAPCLK_IN J6[28]
Input path for the PHI signal to synchronize captures with any delay
from the EVM
~DRDY J6[30] SPI: Data-ready signal for the ADS1285; active-low DRDY
ADC_CLK (input) J6[32] Input for the PHI to sense CLK
ADC_CLK (output) J6[34]
Possible output for the PHI to provide CLK (not supported on the
ADS1285EVM-PDK)
DOUT J6[38] SPI: Serial data output for the ADS1285, or PICO
~RST/PWDN_DAC J6[46] Reset or power-down input pin for the DAC1282
SYNC_DAC J6[48] Synchronize input pin for the DAC1282
WP J6[49] Write protection for the EEPROM
DVDD J6[50] Power-supply source for the digital section of the EVM
SW/TD_DAC J6[52] Switch control input or bitstream input pin for the DAC1282
~CS_DAC J6[54] SPI: Serial port chip select, or CS, for the DAC1282
SDA J6[56] I
2
C serial data for the EEPROM used to identify the EVM
SCL J6[58] I
2
C serial clock for the EEPROM used to identify the EVM
ID_PWR J6[59] Power-supply source for the EEPROM used to identify the EVM
GND J6[60] Ground
www.ti.com Digital Interface
SBAU394A – APRIL 2022 – REVISED SEPTEMBER 2022
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ADS1285EVM-PDK Evaluation Module 9
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