Texas Instruments ADS1285EVM-PDK, Руководство пользователя, Страница: 31 / 40

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GND
MP1
GND
MP2
GND
MP3
GND
MP4
J6
SDA
SCL
GND
5.5V
GND
~DRDY
SCLK
DIN_PHI
CAPCLK_IN
DVDD
PHI Connector
WP
ID_PWR
~RESET
~PWDN
SYNC
GND
~RESET
~PWDN
~RST/PWDN_DAC
ADC_CLK
~DRDY
DOUT
~CS_DAC
Connector for logic analyzer
or external controller
SYNC
SCLK
DIN
DOUT
CS
DRDY
SYNC
RESET
PWDN
GPIO0
MFLAG/GPIO1
CLK
ADS1285_SPI
Connects to 'DC127_ADC' page
DAC1282_SPI
CLK
SYNC
SCLK
DIN
DOUT
CS
SW/TD
RESET/PWDN
Connects to 'DC127_DAC' page
1) FPGA provides CLK output
2) External oscillator drives CLK (default)
Input to PHI >>
<< Output to ADC
CLK Options:
SYNC_DAC
SW/TD_DAC
~CS_ADC
SCLK_PHI
(to FPGA motherboard)
Q
4
D
1
CLK
2
GND
3
VCC
5
U6
SN74AUP1G80DCKT
GND
Clock dividers
GND
1
2
J8
GND
GND
DVDD
On-board clock
GND
Connect jumper across to
select ADC clock frequency.
DNI if using FPGA clock.
Configurable: 1.8V or 3.3V
GPIO1
GPIO0
DIN
DOUT
~RST/PWDN_DAC
SYNC_DAC
Supply range: 1.71V - 3.63V
DIN
SCLK
~CS_ADC
DOUT
GPIO1
~DRDY
GPIO0
SYNC
~PWDN
~RESET
SYNC_DAC
~CS_DAC
~RST/PWDN_DAC
SW/TD_DAC
8 MHz
4 MHz 1
2
3
4
5
J5
GND
External clock
GND
DAC_4MHZ
CAPCLK_OUT
DAC_4MHZ
A0
1
A1
2
A2
3
VSS
4
SDA
5
SCL
6
WP
7
VCC
8
U7
BR24G32FVT-3AGE2
GND
SCL
SDA
GND
WP
EEPROM
ID_PWR
10.0k
R36
~CS_ADC
Gnd
2
Output
3
Tri-state
1
Vdd
4
Y1
ECS-2520MVLC-081.92-BN-TR
Supply range: 0.8V - 3.6V
DVDD
5.5V
DVDD
SCLK_PHI
SW/TD_DAC
~CS_DAC
ADC_CLK
0
R31
0.1uF
C21
0.1uF
C23
0.1uF
C24
1uF
C22
1 2
3 4
5 6
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J9
100k
R30
49.9 R29
49.9 R33
49.9 R34
49.9 R32
49.9
R35
DIN_PHI
GPIO1
GPIO0
DIN_PHI
1 2
3 4
J7
CLK DIS
Figure 9-10. ADS1285EVM-PDK Clock and Interface Schematic
www.ti.com ADS1285EVM-PDK Bill of Materials, PCB Layout, and Schematics
SBAU394A – APRIL 2022 – REVISED SEPTEMBER 2022
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ADS1285EVM-PDK Evaluation Module 31
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