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Overview
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SLAU620D – April 2016 – Revised August 2017
Copyright © 2016–2017, Texas Instruments Incorporated
ADC32RFxx-EVM
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ADC32RFxx-EVM GUI JESD204B Tab Bypass Mode
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HSDC Pro Device Selection LMFS_82820 Mode
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Example Capture from Channel A – Bypass Mode
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ADC32RFxx-EVM GUI LMK04828 PLL1 Page DDC Mode
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ADC32RFxx-EVM Quick Setup View DDC Mode
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ADC32RFxx-EVM GUI JESD204B Configuration Tab DDC Mode
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ADC32RFxx-EVM GUI DDC Configuration Tab
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Connecting to TSW14J56
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HSDC Pro Device Selection LMFS8821 Mode
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Download Firmware
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Resetting the TSW14J56
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Popup Window for Setting HSDC Pro Decimation Factor and NCO Frequency
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Example Capture From Channel A – 8x Decimation Mode
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ADC32RFxx-EVM GUI LMK04828 PLL1 Page DDC Mode
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ADC32RFxx-EVM Quick Setup View DDC Mode
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ADC32RFxx-EVM GUI JESD204B Configuration Tab DDC Mode
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ADC32RFxx-EVM GUI DDC Configuration Tab
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Connecting to TSW14J56
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HSDC Pro Device Selection LMFS8821 Mode
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Download Firmware
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Resetting the TSW14J56
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Popup Window for Setting HSDC Pro Decimation Factor and NCO Frequency
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Example Capture From Channel A – 8x Decimation Mode
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ADC32RF44-EVM Quick Setup View Bypass Mode
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HSDC Pro Device Selection LMFS_8224 Mode
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Example Capture from Channel A – LMFS8224 Mode
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ADC32RF42-EVM Quick Setup View Bypass Mode
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HSDC Pro Device Selection LMFS_42810 Mode
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Example Capture from Channel A – LMFS42810 Mode
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ADC32RFxx EVM GUI With LMX Clock Configuration
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ADC32RFxx EVM GUI With LMK Clock Configuration
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Trademarks
Microsoft, Windows are registered trademarks of Microsoft Corporation.
LabVIEW is a trademark of National Instruments.
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Overview
The ADC32RFxx-EVM is an evaluation module (EVM) designed to evaluate the ADC32RFxx family of
high-speed, JESD204B interface ADCs. The EVM includes an onboard clocking solution (LMK04828),
transformer-coupled analog inputs, full power solution, and easy-to-use software GUI and USB interface.
The following features apply to this EVM:
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Transformer-coupled signal input network allowing a single-ended signal source from 30 MHz to 3000
MHz.
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LMK04828 system clock generator that generates field-programmable gate array (FPGA) reference
clocks for the high-speed serial interface and may optionally be used to generate the ADC sampling
clock.
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Transformer-coupled clock input network to test the ADC performance with a very low-noise clock
source.
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LMX2582 (or LMX2592) clock synthesizer to generate a very low-noise clock source for clocking the
ADC32RFxx ADC.
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High-speed serial data output over a standard FPGA Mezzanine Card (FMC) interface connector.