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ADC32RFxx Internally Generated Clocking
37 SLAU620D – April 2016 – Revised August 2017
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ADC32RFxx-EVM
8.2 ADC32RF45 EVM LMK04828 Clocking
Set up the TSW14J56 and ADC32RF45 as before, with the following exceptions for internally generated
clocking:
1. Verify the clocking selection jumper JP3 is set to the INT position to select the clock to the ADC to be
generated on the EVM, either by the LMX2582 or the LMK04828. The default configuration for the
EVM is for the LMX2582 to be the clock source to the ADC while in internal clock mode. Unsolder the
two AC coupling caps from positions C409 and C410 and solder them into positions C431 and C432.
This disconnects the ADC device clock from the LMX2582 outputs and instead connects the
LMK04828 device clock output to be the clock source to the ADC. There need not be any input to the
J5 external clock SMA. If the LMK04828 is to be synchronized to the timebase of the signal generator
used for the analog input, then connect the 10-MHz sync signal from the signal generator to the
LMK04828 reference input J7. The LMK04828 is still used to supply SYSREF to the ADC and Clock
and SYSREF to the TSW14J56.
2. All but one step to configure the device in this mode are the same as previously described in
Section 3.2 . The only step different is the choice of Clock Source to ADC . That step is to be selected
as shown in Figure 35 . The rest of the steps in Section 3.2 must be followed.
Figure 35. ADC32RFxx EVM GUI With LMK Clock Configuration