3. Click on the “JESD Block Enable" (to enable it). The GUI should look now as shown in
.
Figure 7-5. SYNC is now set low Inside the ADC
7.2.1 Programming the FPGA
This section provides instructions for programming the FPGA.
Launch
Vivado 2019.1
and open the
Hardware Manager
.
Alpha-Data ADC12DJ3200EVMCVAL Start-up Instructions
16
ADC12DJ3200EVMCVAL With Alpha Data Xilinx
®
Kintex Ultrascale Space
Development Kit
SLAU833A – MAY 2020 – REVISED OCTOBER 2020
Copyright © 2020 Texas Instruments Incorporated
