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Table 3-2. ADC-PHI-PRU-EVM Parallel Mode QSH Connector Signal Routing to

the AM64x and AM24x

Signal Name

Pin Number

Signal Name

5.5V

DGND

PRU0_GPIO15

—

PRU0_GPIO14

—

PRU0_GPIO13

—

PRU0_GPIO12

—

PRU0_GPIO11

—

PRU0_GPIO10

—

PRU0_GPIO9

—

PRU0_GPIO8

—

PRU0_GPIO7_LATCH_IN1

—

PRU0_GPIO6

PRU0_GPIO16

PRU0_GPIO5

—

PRU0_GPIO4

—

PRU0_GPIO3

HSE_GPIO0_42

PRU0_GPIO17_SYNC_OUT1

PRU0_GPIO18_LATCH_IN0

—

HSE_GPIO0_35

PRU0_GPIO19_SYNC_OUT0

—

PRU0_GPIO2

HSE_GPIO0_29

PRU0_GPIO1

HSE_GPIO0_24

PRU0_GPIO0

HSE_GPIO0_44

PRU1_GPIO17_SYNC_OUT1

PRU1_GPIO7

Jumper to 44/MCU GPIO

PRU1_GPIO9

PRU1_GPIO10

—

DVDD

HSE_GPIO0_32

PRU1_GPIO14

HSE_GPIO0_34

PRU1_GPIO16

HSE_GPIO0_37

SOC_I2C0_SDA

HSE_GPIO0_39

SOC_I2C0_SCL

HSE_GPIO0_41

DGND

ID PWR

ADC-PHI-PRU-EVM Circuitry

www.ti.com

ADC-PHI-PRU-EVM Evaluation Module

SBAU396 – MAY 2022

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Содержание ADC-PHI-PRU-EVM

Страница 1: ... module EVM Included are the circuit description schematic and bill of materials of the ADC PHI PRU EVM Throughout this document the terms evaluation board evaluation module and EVM are synonymous with the ADC PHI PRU EVM www ti com SBAU396 MAY 2022 Submit Document Feedback ADC PHI PRU EVM Evaluation Module 1 Copyright 2022 Texas Instruments Incorporated ...

Страница 2: ...PRU EVM MUX Schematic Page 10 Figure 4 3 ADC PHI PRU EVM Connectors Schematic Page 11 Figure 4 4 ADC PHI PRU EVM Hardware Schematic Page 12 Figure 4 5 ADC PHI PRU EVM Layout Layer 1 13 Figure 4 6 ADC PHI PRU EVM Layout Layer 2 14 Figure 4 7 ADC PHI PRU EVM Layout Layer 3 15 Figure 4 8 ADC PHI PRU EVM Layout Layer 4 16 List of Tables Table 1 1 ADC PHI PRU EVM Compatible Precision ADC EVMs 3 Table 3...

Страница 3: ...J11 Comments AMC131M03EVM PDK Serial 3 3 V ADC128S102EVM Serial 3 3 V ADS127L11EVM Serial 1 8 V ADS1285EVM PDK Serial 3 3 V ADS131A04EVM Serial 3 3 V ADS131B04 Q1EVM Serial 3 3 V ADS131B26Q1EVM PDK Serial 3 3 V ADS131M04EVM Serial 3 3 V ADS704x 5xEVM Serial 3 3 V ADS8168EVM PDK Serial 3 3 V ADS8332V2EVM PDK PRU1_GPIO17 Serial 3 3 V ADS8353Q1EVM PDK Serial 3 3 V ADS8588SEVM PDK PRU1_GPIO17 Parallel...

Страница 4: ...Three jumpers J2 J9 and J11 on the ADC PHI PRU EVM select the following settings J2 shorts the CONVSTA and CONVSTB signals together for operation with a single CONVST signal J9 configures the MUX to select either serial or parallel mode to communicate with the precision ADC EVM J11 selects either 1 8 V or 3 3 V as the DVDD voltage for the precision ADC EVM Figure 2 1 ADC PHI PRU EVM System Archite...

Страница 5: ...n the HSE connector to the QSH connector As shown in Figure 3 1 J11 selects the DVDD voltage routed to the QSH connector between the 3 3 V and 1 8 V supplies from the AM64x and AM24x HSE connector Figure 3 1 J11 Selects Between the 3 3 V and 1 8 V DVDD Supplies for the ADC Figure 3 2 shows that a TPS61096 boost converter on the ADC PHI PRU EVM converts the 5 0 V HSE output to the 5 5 V output to m...

Страница 6: ... AM64x and AM243x EVMs TMDS64GPEVM and TMDS243GPEVM to communicate with either the parallel or serial precision ADC EVMs Figure 3 4 shows how the J9 jumper sets the voltage level on the MUX device selection pins that route the A side PRU signals from the HSE connector to either the B1 parallel or B2 serial connections on the B side The signal routing to the MUX devices for both parallel and serial...

Страница 7: ...2 21 PRU0_GPIO19_SYNC_OUT0 24 23 26 25 28 27 PRG0_PRU0_GPIO16 30 29 HSE_GPIO0_42 PRU0_GPIO17_SYNC_OUT1 32 31 PRU0_GPIO18_LATCH_IN0 PRU0_GPIO15 34 33 HSE_GPIO0_35 PRU0_GPIO14 36 35 PRU0_GPIO0 38 37 HSE_GPIO0_29 PRU0_GPIO1 40 39 HSE_GPIO0_24 PRU0_GPIO2 42 41 HSE_GPIO0_44 PRU0_GPIO3 44 43 PRU0_GPIO6 PRU0_GPIO4 46 45 PRU0_GPIO7_LATCH_IN1 PRU0_GPIO5 48 47 DVDD 50 49 HSE_GPIO0_32 PRU1_GPIO14 52 51 HSE_G...

Страница 8: ...0_42 PRU0_GPIO17_SYNC_OUT1 32 31 PRU0_GPIO18_LATCH_IN0 34 33 HSE_GPIO0_35 PRU0_GPIO19_SYNC_OUT0 36 35 PRU0_GPIO2 38 37 HSE_GPIO0_29 PRU0_GPIO1 40 39 HSE_GPIO0_24 PRU0_GPIO0 42 41 HSE_GPIO0_44 PRU1_GPIO17_SYNC_OUT1 44 43 PRU1_GPIO7 Jumper to 44 MCU GPIO 46 45 PRU1_GPIO9 PRU1_GPIO10 48 47 DVDD 50 49 HSE_GPIO0_32 PRU1_GPIO14 52 51 HSE_GPIO0_34 PRU1_GPIO16 54 53 HSE_GPIO0_37 SOC_I2C0_SDA 56 55 HSE_GPI...

Страница 9: ...D TP4 DCDC_5V5 TP6 DGND TP7 DGND TP8 DGND TP9 DGND VIN_5V0 VIN_3V3 VIN_1V8 VIN_5V0 VIN_3V3 VIN_1V8 1 2 3 J11 TSW 103 07 G S VIN_1V8 LVI1 1 LVI2 2 VIN 3 SW 4 ILIM 5 EN 6 FB 7 VOSNS 8 VOUT 9 GND 10 HVO2 11 HVO1 12 PAD 13 TPS61096ADSSR U1 2 00k R6 2 7 H µ L1 45 3k R8 10 0k R11 VIN_5V0 DCDC_5V5 GND 10 0k R7 10V 4 7 F µ C4 10 F µ 25V C5 1 50k R4 HSE_GPIO0_30 EVM_ID_PWR VIN_3V3 0 R12 Figure 4 1 ADC PHI ...

Страница 10: ...0B2 33 11B1 32 11B2 31 12B1 30 12B2 29 GND 38 GND 49 NC 28 NC 55 NC 56 SN74CBTLV16292VR U3 VIN_3V3 PRG0_PRU0_GPIO0 PRG0_PRU0_GPIO4 PRG0_PRU0_GPIO19 PRG0_PRU0_GPIO15 PRG0_PRU0_GPIO16 PRG0_PRU1_GPIO17 MODE_SEL MODE_SEL MODE_SEL GND GND PRG0_PRU0_GPIO5 PRG0_PRU0_GPIO2 PRG0_PRU0_GPIO6 PRG0_PRU0_GPIO7 PRG0_PRU0_GPIO8 PRG0_PRU0_GPIO14 PRG0_PRU0_GPIO3 VDD selects S mode GND selects P mode GPIO0p GPIO2p G...

Страница 11: ... PRG0_PRU0_GPIO13 PRG0_PRU0_GPIO14 PRG0_PRU0_GPIO15 PRG0_PRU0_GPIO16 PRG0_PRU0_GPIO17 PRG0_PRU0_GPIO18 PRG0_PRU1_GPIO0 PRG0_PRU1_GPIO1 PRG0_PRU1_GPIO2 PRG0_PRU1_GPIO3 PRG0_PRU1_GPIO4 PRG0_PRU1_GPIO5 PRG0_PRU1_GPIO6 PRG0_PRU1_GPIO7 PRG0_PRU1_GPIO8 PRG0_PRU1_GPIO9 PRG0_PRU1_GPIO10 PRG0_PRU1_GPIO11 PRG0_PRU1_GPIO12 PRG0_PRU1_GPIO13 PRG0_PRU1_GPIO14 PRG0_PRU1_GPIO15 PRG0_PRU1_GPIO16 PRG0_PRU1_GPIO17 P...

Страница 12: ... otherwise specified Variant Label Table Variant Label Text 001 MPU PADC adapter card Logo1 CE Mark LOGO PCB Logo4 WEEE logo 1 H1 NY PMS 440 0025 PH DNP 1 H2 NY PMS 440 0025 PH DNP LOGO PCB Logo3 FCC disclaimer SH1 1 H3 NY PMS 440 0025 PH DNP 1 H4 NY PMS 440 0025 PH DNP SH2 SH3 MP1 29300 MP2 29300 Standoff hardware In addition to 29300 screws 970300151 standoffs 4692 washers 728 rubber feet and 29...

Страница 13: ...ate the layout for the ADC PHI PRU EVM Figure 4 5 ADC PHI PRU EVM Layout Layer 1 www ti com Schematics PCB Layout and Bill of Materials SBAU396 MAY 2022 Submit Document Feedback ADC PHI PRU EVM Evaluation Module 13 Copyright 2022 Texas Instruments Incorporated ...

Страница 14: ... ADC PHI PRU EVM Layout Layer 2 Schematics PCB Layout and Bill of Materials www ti com 14 ADC PHI PRU EVM Evaluation Module SBAU396 MAY 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Страница 15: ... ADC PHI PRU EVM Layout Layer 3 www ti com Schematics PCB Layout and Bill of Materials SBAU396 MAY 2022 Submit Document Feedback ADC PHI PRU EVM Evaluation Module 15 Copyright 2022 Texas Instruments Incorporated ...

Страница 16: ... ADC PHI PRU EVM Layout Layer 4 Schematics PCB Layout and Bill of Materials www ti com 16 ADC PHI PRU EVM Evaluation Module SBAU396 MAY 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Страница 17: ...4 R5 4 1 50 kΩ RES 1 50 kΩ 1 0 1 W AEC Q200 Grade 0 0603 0603 CRCW06031K50FKEA Vishay Dale R3 1 0 Ω RES 0 5 0 1 W 0603 0603 MCR03EZPJ000 Rohm R6 1 2 00 kΩ RES 2 00 kΩ 1 0 063 W AEC Q200 Grade 0 0402 0402 CRCW04022K00FKED Vishay Dale R7 R11 2 10 0 kΩ RES 10 0 kΩ 1 0 05 W 0201 0201 RC0201FR 0710KL Yageo America R8 1 45 3 kΩ RES 45 3 kΩ 1 0 063 W AEC Q200 Grade 0 0402 0402 CRCW040245K3FKED Vishay Dal...

Страница 18: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Страница 19: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Страница 20: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Страница 21: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Страница 22: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Страница 23: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

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