Texas Instruments 2N7001TEVM, Руководство пользователя, Страница: 2 / 10

Introduction
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2 SCEU013 – May 2018
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Copyright © 2018, Texas Instruments Incorporated
2N7001T Evaluation Module
1 Introduction
The 2N7001T is a new single bit, unidirectional voltage translator from Texas Instruments. It uses two
individually configurable power-supply rails which can be configured from 1.65 V to 3.6 V. This makes the
2N7001T suitable for translation between 1.8 V, 2.5 V, and 3.3 V. The 2N7001TEVM enables the
evaluation of this single bit voltage translator.
1.1 Features
The 2N7001T has two configurable supply pins that allow it to up-translate or down-translate from 1.65 V
to 3.6 V. The A input pin has thresholds defined by the V
CCA
pin. The B output pin has thresholds defined
by the V
CCB
pin. The glitch-free power sequence allows the two supplies to be ramped up or down, in any
order, without causing a glitch on the I/Os. An example of this is when an output waveform momentarily
transitions from Logic Low to Logic High during device power up. Glitches like this can be misinterpreted
by a peripheral as a valid data bit which can trigger a false reset, failed configuration, or invalid data
initialization.
The 2N7001T is specified for partial-power-down applications using I
OFF
. The I
OFF
circuitry disables the
output which prevents current back flow through the device. This prevents the device from being damaged
when powered down. The V
CC
isolation feature ensures that if either V
CC
supplies is at 100 mV or less,
then the output on Pin B is in a high-impedance state.
This EVM is designed to support the 2N7001T in DCK and DPW packages. For more information on the
DPW package, see the
Designing and Manufacturing with TI's X2SON Packages application report.
Figure 1. 2N7001TEVM Board
1.2 Hardware Description
1.2.1 Passive Components
The 2N7001TEVM has several passive components located on the board. C1 and C2 are 0.1 µF bypass
capacitors for V
CCA
and V
CCB
. R1 and R2 are 0 Ω jumper resistors. These resistors can be removed to
isolate the I/O of the 2N7001TDPWR device from the SMB connectors (J3 and J4) and the
2N7001TDCKR I/O device from the headers (J1 and J2). By default, these resistors are populated to
ensure both devices share inputs and outputs to both the SMB connectors and headers.