Tews Technologies TPMC467-10R, Руководство пользователя

Страница: 19 / 30

5.2.1 Accessing XR17D154 MPIO-Pins
The MPIO Registers are accessible at PCI Base Address 0 + Device Configuration Register Offset.
Address
Offset Register Description Access Reset
Value
0x08F MPIOINT MPIO Interrupt Mask R/W 0x00
0x090 MPIOLVL MPIO Level Control R/W 0x00
0x091 MPIO3T MPIO Output Pin Tri-state Control R/W 0x00
0x092 MPIOINV MPIO Input Polarity Select R/W 0x00
0x093 MPIOSEL MPIO Input/Output Select R/W 0xFF
Table 5-4 : MPIO Device Configuration Registers
MPIOINT, MPIOLVL and MPIO3T must be left at their default values. MPIOSEL must be set to 0x80 to
configure MPIO[6-0] pins as outputs and MPIO[7] as input. MPIOLVL sets the output level of the MPIO
output pins and is used to write on the CPLD-bus.
5.2.2 CPLD-Bus Protocol
5.2.2.1 Write
A CPLD register write access starts with setting CEN to ‘1’. This resets the CPLD’s internal state-
machine. Before the first clock pulse is issued, ADR and DATAOUT have to be set; R/W# must be left
‘0’. The first rising edge of CLK samples the ADR bits and the DATAOUT bit. ADR determines which
internal register is accessed. The following 6 rising edges of CLK sample the remaining data bits,
additional CLK pulses are ignored. Setting CEN back to ‘0’ completes the access and the
configuration of the transceivers will be updated.
CLK
DATAOUT
ADR
CEN
Address
Bit5 Bit4 Bit3 Bit2 Bit1 Bit6
Sample address & first data bit
Reset internal state machine Write to outputs
R/W
DATAIN
Bit0
Figure 5-2 : CPLD-Bus Write
Example (pseudocode):
Write value 0x05 to CPLD address 0x03
define MPIOLVL 0x90;
define MPIOSEL 0x93;
void Write_XR17D154(int address, int value);
TPMC467 User Manual Issue 1.0.4 Page 19 of 30