Bit
Symbol
Description
Access
Reset
Value
2
RENA
Auto RS485 Receiver Enable
When the Auto RTS Control feature of the XR17D154 is used
in half duplex configurations, this bit can be used to inhibit the
reception of an echo of the own data transmission
‘0’: Normal operation (receiver is always enabled)
‘1’: Inhibit echo reception (receiver is disabled during data
transmission)
R/W
0
1
HDPLX
Selectable Mode Functionality. Operates in full-duplex mode
when low; operates in half-duplex mode when high.
‘0’: Full-duplex
‘1’: Half-Duplex
R/W
0
0
RS485/
RS232#
Selectable Mode Functionality. Operates as RS485 with a
logic-level high; operates as RS232 with a logic-level low.
‘0’: RS232
‘1’: RS485
R/W
0
Table 5-2 : Channel Control Register
5.2 CPLD Access
The CPLD it is connected to the MPIO-pins of the XR17D154 to provide access to the control
registers.
PC
I Bu
s
MP
IO
XR17D154
CPLD
Transceiver
CH0
CH1
CH2
CH3
Reg. CH0
Reg. CH1
Reg. CH2
Reg. CH3
Figure 5-1 : CPLD-Bus Block Diagram
The MPIO-pins form a simple bus to the CPLD. The following chart gives an overview about the MPIO
pin assignment:
MPIO Pin
Direction
Function
MPIO[0]
Output
CEN – Chip Enable
MPIO[1]
Output
R/W# - Read/Write
Low: Write to Address
High: Read from Address
MPIO[2]
Output
CLK – Clock
MPIO[5-3]
Output
ADR – Register Address
MPIO[6]
Output
DATAOUT – Serial Data Output
MPIO[7]
Input
DATAIN – Serial Data Input
Table 5-3 : MPIO Pins
TPMC467 User Manual Issue 1.0.4
Page 18 of 30
