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TMPE633 User Manual Issue 1.0.3

Page 20 of 25

7.2.2 I/O Connector (X2)

Pin-Count

30

Connector Type

Molex Pico-Clasp, dual row straight header, with lock

Source & Order Info

501190-3017

Mating Part

501189-3010

The I/O connector will exceed the available PCI Express Mini Card components height. Check
carefully if you application provides enough spacing for a TMPE633.

Pin Assignment

Description

Pin

Pin

Description

TTL

(-10R)

Diff.

(-11R/-12R)

TTL

(-10R)

Diff.

(-11R/-12R)

GND

GND

1

2

GND

GND

I/O_0

I/O_0+

3

4

I/O_1

I/O_0-

I/O_2

I/O_1+

5

6

I/O_3

I/O_1-

I/O_4

I/O_2+

7

8

I/O_5

I/O_2-

I/O_6

I/O_3+

9

10

I/O_7

I/O_3-

I/O_8

I/O_4+

11

12

I/O_9

I/O_4-

I/O_10

I/O_5+

13

14

I/O_11

I/O_5-

I/O_12

I/O_6+

15

16

I/O_13

I/O_6-

I/O_14

I/O_7+

17

18

I/O_15

I/O_7-

I/O_16

I/O_8+

19

20

I/O_17

I/O_8-

I/O_18

I/O_9+

21

22

I/O_19

I/O_9-

I/O_20

I/O_10+

23

24

I/O_21

I/O_10-

I/O_22

I/O_11+

25

26

I/O_23

I/O_11-

I/O_24

I/O_12+

27

28

I/O_25

I/O_12-

GND

GND

29

30

GND

GND

Figure 7-3 : I/O Connector Pin Assignment

I/O_x signals correspond to the DIOx/OEx FPGA pins.

The DIOx/OEx FPGA pins for the I/O_x signals that are not shown in the table are not connected on this
build option (i.e. I/O_13 to I/O_25 are not connected for differential board variants like TMPE633-11R or
TMPE633-12R).

Содержание TMPE633

Страница 1: ...onfigurable FPGA with Digital I O PCIe Mini Card Version 1 0 User Manual Issue 1 0 3 April 2020 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 1...

Страница 2: ...LOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of...

Страница 3: ...of 25 Issue Description Date 1 0 0 Initial Issue December 2015 1 0 1 Added TA308 May 2016 1 0 2 Clarification Chapters Product Description and Example Design May 2016 1 0 3 Corrected Mating Part numb...

Страница 4: ...0 4 3 4 3 1 SPI Flash 10 4 3 2 Configuration via JTAG 11 4 3 3 Generate Spartan 6 Configuration Data 11 Clocking 11 4 4 4 4 1 FPGA Clock Sources 11 Digital I O Interface 12 4 5 4 5 1 TTL I O Interface...

Страница 5: ...XRS CONNECTOR PIN ASSIGNMENT 21 FIGURE 7 5 TMPE633 CONNECTED TO A PROGRAMMER VIA TA308 21 List of Tables TABLE 2 1 TECHNICAL SPECIFICATION 7 TABLE 4 1 TMPE633 FPGA FEATURE OVERVIEW 9 TABLE 4 2 FPGA BA...

Страница 6: ...onnector The User FPGA is configured by a SPI flash An in circuit debugging option is available via a JTAG header for read back and real time debugging of the FPGA design using Xilinx ChipScope User a...

Страница 7: ...485 lines TMPE633 12R 13 differential M LVDS lines I O Transceiver TMPE633 10R 74LVC2G241 or compatible TMPE633 11R 65HVD75D or compatible TMPE633 12R 65LVDM176D or compatible I O Connector 30 pol Pic...

Страница 8: ...Card module is sensitive to static electricity Packing unpacking and all other module handling has to be done in an ESD EOS protected Area Height Restrictions 3 2 The I O connector will exceed the av...

Страница 9: ...6 2 Table 4 1 TMPE633 FPGA Feature Overview The FPGA is equipped with 4 I O banks and 2 MGT multi gigabit transceiver One of the MGTs can be connected to an Endpoint Block for PCI Express Bank VCCO VR...

Страница 10: ...rtan 6 FPGA can be configured by the following interfaces Master Serial SPI Flash Configuration Interface JTAG Interface via JTAG Header On delivery the SPI configuration Platform Flash contains the T...

Страница 11: ...r Clock g ExtMasterCclk_en enable Setup External Master Clock Devision g ExtMasterCclk_divide 1 To use the maximum data transfer speed of the User FPGA SPI Configuration Flash the SPI Configuration Bu...

Страница 12: ...IN OUT LVCMOS33 1 8 SLOW DIO 8 V12 IN OUT LVCMOS33 2 8 SLOW DIO 9 U7 IN OUT LVCMOS33 2 8 SLOW DIO 10 R7 IN OUT LVCMOS33 2 8 SLOW DIO 11 N6 IN OUT LVCMOS33 2 8 SLOW DIO 12 U13 IN OUT LVCMOS33 2 8 SLOW...

Страница 13: ...8 SLOW OE 22 R3 OUTPUT LVCMOS33 2 8 SLOW OE 23 U5 OUTPUT LVCMOS33 2 8 SLOW OE 24 V6 OUTPUT LVCMOS33 2 8 SLOW OE 25 T6 OUTPUT LVCMOS33 2 8 SLOW Table 4 7 Digital I O Interface 4 5 1 TTL I O Interface E...

Страница 14: ...the desired voltage can be adjusted directly from the User FPGA The user must ensure that valid signals are always driven CNT Lines Description Spartan 6 Pins SEL 1 0 11 pull down 10 pull up to 3 3 V...

Страница 15: ...Interface Please note that each TMPE633 M LVDS line provides its own termination If more than four lines are connected together some termination resistors must be removed The actual data transmission...

Страница 16: ...oling apply Forced air cooling is recommended during operation The Spartan 6 FPGA has no heatsink mounted If additional cooling is required the TMPE633 can be equipped with a heatsink for example a Fi...

Страница 17: ...onfiguration can be triggered by the FPGA application itself or during the initial FPGA configuration when an error occurs Fallback Multiboot The latter can be used to implement safe in field updates...

Страница 18: ...Issue 1 0 3 Page 18 of 25 7 I O Connectors This chapter provides information about user accessible on board connectors Overview 7 1 X1 System Connector X2 I O Connector X3 JTAG Connector Figure 7 1 I...

Страница 19: ...5 46 LEP_WPAN GND 43 44 LEP_WLAN 3 3Vaux 41 42 LEP_WWAN 3 3Vaux 39 40 GND GND 37 38 USB_D GND 35 36 USB_D PETp0 33 34 GND PETn0 31 32 SMB_DATA GND 29 30 SMB_CLK GND 27 28 1 5V PERp0 25 26 GND PERn0 23...

Страница 20: ...I O_1 5 6 I O_3 I O_1 I O_4 I O_2 7 8 I O_5 I O_2 I O_6 I O_3 9 10 I O_7 I O_3 I O_8 I O_4 11 12 I O_9 I O_4 I O_10 I O_5 13 14 I O_11 I O_5 I O_12 I O_6 15 16 I O_13 I O_6 I O_14 I O_7 17 18 I O_15 I...

Страница 21: ...provides a Programming Kit TA308 which includes a XSR cable and an adapter module that provides a Xilinx USB Programmer II compatible 2 mm shrouded header Pin Description 1 GND 2 TCK 3 TMS 4 TDI 5 TDO...

Страница 22: ...ed on the TMPE633 Owner TEWS TECHNOLOGIES GmbH Am Bahnhof 7 D 25469 Halstenbek Tel 49 0 4101 4058 0 Fax 49 0 4101 4058 19 e mail support tews com Copyright c 2015 TEWS TECHNOLOGIES GmbH History Versio...

Страница 23: ...eference Clock CLK_P net REFCLK_N loc A8 Bank 101 100 MHz PCI Express Reference Clock CLK_N Additional Constraints NET gt_refclk_out 0 TNM_NET GT_REFCLK_OUT TIMESPEC TS_GT_REFCLK_OUT PERIOD GT_REFCLK_...

Страница 24: ...3 loc V15 Bank 2 net OE 4 loc R11 Bank 2 net OE 5 loc U15 Bank 2 net OE 6 loc E16 Bank 1 net OE 7 loc U11 Bank 2 net OE 8 loc V11 Bank 2 net OE 9 loc V4 Bank 2 net OE 10 loc T7 Bank 2 net OE 11 loc T3...

Страница 25: ...t Location Constraints net PULL_SEL 0 loc F14 Bank 1 net PULL_SEL 1 loc F16 Bank 1 net PERST_n loc E8 Bank 0 PCI Express Reset Section General Purpose I O Location Constraints config prohibit C15 Bank...

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