TMPE633 User Manual Issue 1.0.3
Page 14 of 25
With the pull voltage set to 5 V, the digital I/O can weakly drive a higher voltage than 3.3 V by setting the
output to tri-state. This can be useful when connecting to a standard 5 V CMOS logic input, where a high
level of minimum 3.5 V is required. Drive DIO constant low and use OE to toggle the output.
With the pull voltage set to GND, a pull-down functionality is implemented. Drive DIO constant high and use
OE to toggle the output.
Pull Option
DIO
OE
Output
Remark
No pull-up or pull-down
0
1
1
1
1
1
Pull-up to 3.3 V
0
1
0
1
1
1
Driven to 3.3 V
-
0
1
Pulled to 3.3 V
Pull-up to 5 V
0
1
0
-
0
1
Pulled to 5 V
Pull-down to GND
-
0
0
Pulled to GND
1
1
1
Table 4-8 : I/O Pull Options
If the pull resistors float, the user should keep in mind that the I/O Lines are connected via their pull resistors.
The normal behavior is that the User FPGA code controls the I/O Pull Configuration depending on User
FPGA I/O Function. The SEL signals are connected to an analog multiplexer. With this multiplexer the
desired voltage can be adjusted directly from the User FPGA. The user must ensure that valid signals are
always driven.
CNT Lines
Description
Spartan-6 Pins
SEL[1:0]
11 : pull-down
10 : pull-up to 3.3 V
01 : pull-up to 5 V
00 : No pull-up or pull-down
F16, F14
Table 4-9 : I/O Pull Configuration
4.5.1.1 Output Level & Output Current
Because of the 47 ohm series resistor, there is a reduced high-level voltage at the I/O pin when the output
buffer sources a noticeable current to the external load while driving a high-level. To maintain a proper TTL
high level, the recommended maximum I/O source current is 15 mA.
There is also an increased low-level voltage at the I/O pin when the output buffer sinks a noticeable current
from the external load while driving a low-level. To maintain a proper TTL low level, the recommended
maximum I/O sink current is 6 mA.
For achieving a 5 V CMOS high-level voltage (V
OH
>= 3.5 V), the external load should be high impedance. If
there would be a low impedance path to ground on the I/O load, this may result in a voltage divider with the
on-board pull resistor, significantly reducing the high-level voltage at the I/O pin. To maintain a proper 5 V
CMOS high level, the I/O load (leakage) current should not exceed 250 µA.
