TIP670 User Manual Issue 1.3
Page 14 of 19
6.2 Initialization of the Watchdog Function
On the TIP670 port C and counter timer 3 of the Z8536 are wired in way, that a watchdog function can
be programmed into the TIP670. This watchdog is retriggered with every access to the TIP670. If
there is no access within a previously programmed time frame, the watchdog will automatically disable
the output lines.
If the TIP670 is accessed after the watchdog timer has expired, the output lines will return to its
original state.
For initialization of the watchdog function proceed as follow:
•
Write 0x1E to CIOCSR
This selects the Counter/Timer 3 Mode Specification Register (CT3MO) for the next operation
•
Write
0x55
to CIOCSR
Writing 0x55 into CT3MO will configure counter/timer 3 to single cycle, retrigger enable, external
output, one shot
•
Write 0x1A to CIOCSR
This selects the Counter/Timer3 Preload MSB Register (CT3PM) for the next operation
•
Write 0xF0 to CIOCSR
Writing 0xF0 into CT3PM will load the first half of the watchdog time out time of ‘0xF000’ which is
just an example for approx. 30ms
•
Write 0x1B to CIOCSR
This selects the Counter/Timer3 Preload LSB Register (CT3PL) for the next operation
•
Write 0x00 to CIOCSR
Writing 0x00 into CT3PL will load the second half of the watchdog time out time of ‘0xF000’ which
is just an example for approx. 30ms
•
Write 0x06 to CIOCSR
This selects the Port C Data Direction Register (PCDD) for the next operation
•
Write 0x04 to CIOCSR
Writing 0x04 into PCDD configures bit 2 as an input for retrigger
•
Write 0x01 to CIOCSR
This selects the Master Configuration Control Register (MCCR) for the next operation
•
Write 0x84 to CIOCSR
Writing 0x84 into MCCR will enable port A and B
•
Write 0x0F to CIOCSR
This selects the Port C Data Register (PCDR) for the next operation
•
Write 0x70 to CIOCSR
Writing 0x70 into PCDR configures bit 3 as an writable output
