TDRV004-SW-82 - Linux Device Driver
Page 51 of 62
BAR
PCI Address-Type
TDRV004_RESOURCE
0
IO
(reserved)
TDRV004_RES_IO_1
1
MEM
(reserved)
TDRV004_RES_MEM_1
2
MEM
(used by VHDL Example)
TDRV004_RES_MEM_2
3
IO
(not implemented by default)
TDRV004_RES_IO_2
4
IO
(not implemented by default)
TDRV004_RES_IO_3
5
MEM
(not implemented by default)
TDRV004_RES_MEM_3
The PLX PCI9030 default configuration utilizes only BAR0 to BAR2.
Offset
Specifies the offset into the memory or I/O space specified by
Resource
.
Size
This value specifies the amount of data items to write.
pData
The values are copied from this buffer. It must be large enough to hold the specified
amount of data.
EXAMPLE
#include “tdrv004api.h”
TDRV004_HANDLE
hdl;
TDRV004_STATUS
result;
TDRV004_MEMIO_BUF
pMemIoBuf;
unsigned short
*pValues;
int
BufferSize;
/*
** write 10 16bit words to MemorySpace 2, offset 0x00
** allocate enough memory to hold the data str write data
*/
BufferSize
= ( sizeof(TDRV004_MEMIO_BUF) + 10*sizeof(unsigned short) );
pMemIoBuf
= (TDRV004_MEMIO_BUF*)malloc( BufferSize );
pMemIoBuf->Size
= 10;
pMemIoBuf->Resource
= TDRV004_RES_MEM_2;
pMemIoBuf->Offset
= 0;
pValues
= (unsigned short*)pMemIoBuf->pData;
pValues[0]
= 0x0001;
pValues[1]
= 0x0002;
…
