Teridian 73S8024C, Руководство пользователя

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73S8024C Demo Board User Manual UM_8024C_061
6 Rev. 1.3
2 Basic Connections
The basic connections to the demo board are described below and shown in Figure 2.
1. Connect power supply: Apply 3.3 V to pin 10 of J4.
2. Control signals to the device can be connected through J2 and J4 (see Figure 2 and the Electrical
Schematic, Figure 5 ).
3. To set the clock frequency with an external clock source:
•
Set JP1 to the SCLK setting.
•
Apply clock source to pin 1 of J2.
•
Apply 3.3V (1) or GND (0) to CLKDIV1 and CLKDIV2 pins to set the desired clock rate as follows:

CLKDIV1 = CLKDIV2 = 0 clock frequency = SCLK/8

CLKDIV1 = 0, CLKDIV2 =1 clock frequency = SCLK/4

CLKDIV1 = 1, CLKDIV2 =0 clock frequency = SCLK

CLKDIV1 = CLKDIV2 = 1 clock frequency = SCLK/2
4. To set the clock frequency using crystal Y1:
•
The crystal included on the demo board is 12 MHz.
•
Set JP1 to XTAL position.
•
Apply 3.3V (1) or GND (0) to CLKDIV1 and CLKDIV2 pins to set the desired clock rate as follows:

CLKDIV1 = CLKDIV2 = 0 clock frequency = 1.5 MHz

CLKDIV1 = 0, CLKDIV2 =1 clock frequency = 3 MHz

CLKDIV1 = 1, CLKDIV2 =0 clock frequency = 12 MHz

CLKDIV1 = CLKDIV2 = 1 clock frequency = 6 MHz
Figure 2: 73S8024C Demo Board Basic Connections
1
2
CKDIV2
CKDIV1
RSTIN
CMDVCC
GND
VDD
PWRDN
5V/
#V
GND
SCLK
OFF
I/OUC
AUX1UC
AUX2UC
External clock source. JP1 must be in
position SCLK when using an
external clock. Otherwise, pin SCLK
can be left open.
V
PC
Power
Supply:
Configure JP2
to 3.3V
V
DD
Power Supply:
+2.7V to +3.6V
(3.3V Typ.) / 50mA
Note: CLKSTOP and CLKLEV
can be left NC if unused.
5V/
#V
too, for 5V cards only.