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UM_8024C_061 

73S8024C Demo Board User Manual 

Rev. 1.3 

13 

5  73S8024C Demo Board Schematics, PCB Layouts and Bill of Materials 

5.1  Schematic 

USR3

CLK

GND

JP6

1
2
3

PGND

5V

C4

22pF

J4

TSM_110_01_L_SV

1
2
3
4
5
6
7
8
9

10

SC4

3.3V

R8
Ru

TP6

1
2

VDD

USR5

C4

VPC

R10
Ru

Resistors

not

populated

+

C10

10uF

3.3V

GND

C11

0.1uF

Connectors are positioned to allow

multiple 8024C boards (stacking) to a

73S1121F evaluation board.  Also used for

connecting external signals when used as a

stand alone board.

JP4

HEADER LOCK 3

1
2
3

CLKDIV1

GND

USR2

+

C1

10uF

JP2 must be
set to 3.3V

Card detection

switches are

normally open

CARD DETECT
POLARITY SELECT

I/O

VDD

R11
Rd

SIO

L1

10uF

R2

0

R5

R7

0

R12
Rd

C8

GND

5.0V

TP7

1
2

JP2

1

2

3

R13
Rd

USR1

3.3V

C2

0.1uF

R6

OFFB

R4

0

C8

0.1uF

C1, C2, C8, C9 and L1 must be

placed within 5mm of the U1 pins

and connected by thick track

(wider than 0.5mm)

5V

S_C8

Resistors not
populated

U1

73S8024C

1
2
3
4
5
6
7

12

8
9

10
11

13
14

15

16

17

18

19

20

21

22

23

28
27

25
24

26

CLKDIV1
CLKDIV2
5V3V
GND_4
LIN
VPC
NC

AUX2

PWRDN
PRES
PRES
I/O

AUX1
GND_14

CLK

RST

VCC

VDDF_ADJ

CMDVCC

RSTIN

VDD

GND

OFF

AUX2UC
AUX1UC

XTALOUT

XTALIN

I/OUC

JP3 must be
set to 3.3V

J5

Smart Card Connector

1

2

3

4

5

6

7

8

9

1

0

VC

C

R

ST

C

L

K

C4

GN

D

VPP

I/

O

C8

SW

-1

SW

-2

SIO

TP2

1

2

CLKDIV2

JP3

1
2
3

3.3V

J2

TSM_110_01_L_SV

1
2
3
4
5
6
7
8
9

10

+

C3

10uF

5.0V

TP8

1
2

SC8

5V3VB

3.3V

TP4

1
2

PIN18

Signal names

refer to

73S1121F

Evaluation

board.

GND

NC

USR6

JP5

1
2
3

VDD

C5

22pF

5V

XTALIN
SELECT

GND

PWRDN

USR4

J1

SSM_110_L_SV

1
2
3
4
5
6
7
8
9

10

SCLK

R9
Ru

TP1

1
2

SCLK

VDD
SELECT

Signal names

refer to

73S1121F

Evaluation

board.

VDD

CMDVCCB

TP5

1
2

XTAL

TP3 to TP8 to be placed

very close to the pads

of J5

R3

J6

SIM/SAM Connector

1

2

3

4

5

6

7

8

C1

C2

C3

C5

C6

C7

SW

1

SW

2

SCLK

+5V

TP3

1
2

RSTIN

L1 must be

placed close

to pin 5

VPC
SELECT

INT2

PRESB

S_C4

+5V

JP1

1
2
3

GND

PRES

J3

SSM_110_L_SV

1
2
3
4
5
6
7
8
9

10

VCC

C9

0.47uF

+3.3V

VDD

C13

27pF

R1

RST

Y 1

12.000MHz

1

4

C12

27pF

5.0V

USR7

USR0

 

Figure 5: 73S8024C Demo Board Electrical Schematic  

Содержание 73S8024C

Страница 1: ...Simplifying System IntegrationTM 73S8024C Demo Board User Manual November 11 2009 Rev 1 3 UM_8024C_061...

Страница 2: ...the Company s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions The company assumes no responsibility for any errors which may appear in this document reserves...

Страница 3: ...mended Operating Conditions and Absolute Maximum Ratings 9 3 3 73S8024C Pin Description 9 3 4 73S8024C Pinout 11 4 Design Considerations 12 4 1 General Layout Rules 12 4 2 Optimization for Compliance...

Страница 4: ...Demo Board Top Signal Layer 16 Figure 9 73S8024C Demo Board Middle Layer 1 Ground Plane 16 Figure 10 73S8024C Middle Layer 2 Supply Plane 17 Figure 11 73S8024C Demo Board Bottom Signal Layer 17 Tables...

Страница 5: ...ned to comply with the EMV 2000 Specification Version 4 0 73S8024C Demo Boards can easily be modified to comply with NDS specifications by replacing a few external components that are highlighted in t...

Страница 6: ...lock frequency SCLK CLKDIV1 CLKDIV2 1 clock frequency SCLK 2 4 To set the clock frequency using crystal Y1 The crystal included on the demo board is 12 MHz Set JP1 to XTAL position Apply 3 3V 1 or GND...

Страница 7: ...at contacts must face up 11 J6 Smart Card Connector SIM SAM smart card format connector J6 is wired in parallel to the smart card connector J5 underneath the PCB No SIM SAM should be inserted when usi...

Страница 8: ...triggers a card deactivation sequence By default the resistors R1 and R3 are not connected This provides a VDD fault level of 2 3V typical internally set to the 73S8024C Refer to the 73S8024C Data She...

Страница 9: ...HBM condition 3 pulses each polarity referenced to ground 3 3 73S8024C Pin Description Table 4 73S8024C Card Interface Pins Name Pin Description I O 11 Card I O Data signal to from card Includes a pul...

Страница 10: ...lection Logic one selects 5 volts for VCC and card interface logic low selects 3 volt operation When the part is to be used with a single card voltage this pin should be tied to either GND or VDD Howe...

Страница 11: ...CLKDIV1 CLKDIV2 5V V GND VPC PRES PRES I O AUX2 AUX1 GND AUX2UC AUX1UC I OUC XTALIN XTALOUT OFF VDD RSTIN CMDVCC VCC RST CLK NC LIN PWRDN VDDF_ADJ GND 73S8024C 1 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

Страница 12: ...smart card connector and directly take other end to ground 4 2 Optimization for Compliance with EMV and NDS The default configuration of the demo board contains a 27 pF capacitor C12 from the CLK pin...

Страница 13: ...4 5 6 7 12 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 28 27 25 24 26 CLKDIV1 CLKDIV2 5V3V GND_4 LIN VPC NC AUX2 PWRDN PRES PRES I O AUX1 GND_14 CLK RST VCC VDDF_ADJ CMDVCC RSTIN VDD GND OFF AUX2UC AU...

Страница 14: ...11 36 ND PZC36SAAN Sullins 8 1 JP4 Header Lock 3 3pins 2 54 mm pitch WM2701 ND 22 11 2032 Molex 9 2 J1 J3 SSM_110_L_SV SSM_110_L_SV X SSM_110_L_SV Samtec 10 2 J2 J4 TSM_110_01_L_SV TSM_110_01_L_SV X T...

Страница 15: ...UM_8024C_061 73S8024C Demo Board User Manual Rev 1 3 15 5 3 PCB Layouts Figure 6 73S8024C Demo Board Top View Figure 7 73S8024C Demo Board Bottom View...

Страница 16: ...73S8024C Demo Board User Manual UM_8024C_061 16 Rev 1 3 Figure 8 73S8024C Demo Board Top Signal Layer Figure 9 73S8024C Demo Board Middle Layer 1 Ground Plane...

Страница 17: ...UM_8024C_061 73S8024C Demo Board User Manual Rev 1 3 17 Figure 10 73S8024C Middle Layer 2 Supply Plane Figure 11 73S8024C Demo Board Bottom Signal Layer...

Страница 18: ...ts are available from Teridian Semiconductor Corporation 73S8024C Data Sheet 73S8024C Demo Board User Manual this document Teridian 73S8024C versus Philips TDA8024T Application Note 8 Contact Informat...

Страница 19: ...First publication 1 1 8 2 2004 Minor corrections 1 2 8 23 2005 Added new logo 1 3 11 11 2009 Added Section 1 1 Package Contents Added Section 1 2 Safety and ESD Notes Added Section 6 Ordering Informa...

Страница 20: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Maxim Integrated 73S8024C DB...

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