10
Chapter 3
Chapter 3
Chapter 3
Chapter 3
Using
Using
Using
Using VEEK
VEEK
VEEK
VEEK----MT
MT
MT
MT----C5SOC
C5SOC
C5SOC
C5SOC
This section describes the detailed information of the components, connectors, and pin assignments
of the VEEK-MT-C5SOC.
3
3
.
.
1
1
U
U
s
s
i
i
n
n
g
g
t
t
h
h
e
e
C
C
y
y
c
c
l
l
o
o
n
n
e
e
®
®
V
V
S
S
X
X
S
S
o
o
C
C
F
F
P
P
G
G
A
A
The VEEK-MT-C5SOC is composed of Cyclone V SoC development board and 7" touch panel
daughter card. In this combination, the Cyclone V SoC development board which equips the FPGA
device is considered as the main part. Therefore, it can refer to the User Guide
(
http://www.altera.com/literature/ug/ug_cv_soc_dev_kit.pdf
) of Cyclone V SoC development board
on the FPGA device configuration and board setup.
3
3
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2
2
U
U
s
s
i
i
n
n
g
g
t
t
h
h
e
e
7
7
”
”
L
L
C
C
D
D
C
C
a
a
p
p
a
a
c
c
i
i
t
t
i
i
v
v
e
e
T
T
o
o
u
u
c
c
h
h
S
S
c
c
r
r
e
e
e
e
n
n
The VEEK-MT-C5SOC features a 7-inch capacitive amorphous TFT-LCD panel. The LCD touch
screen offers resolution of (800x480) to provide users the best display quality for developing
applications. The LCD panel supports 24-bit parallel RGB data interface.
The VEEK-MT-C5SOC is also equipped with a Touch controller, which can read the coordinates of
the touch points through the serial port interface of the Touch controller.
To display images on the LCD panel correctly, the RGB color data along with the data enable and
clock signals must act according to the timing specification of the LCD touch panel as shown in
Table 3-1. Table 3-2
gives the pin assignment information of the LCD touch panel.
Table 3-1 LCD timing specifications
ITEM
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
DCLK
Dot Clock
1/tCLK
33
MHZ
DCLK pulse duty
Tcwh
40
50
60
%
DE
Setup time
Tesu
8
ns
Hold time
Tehd
8
ns
Horizontal period
tH
1056
tCLK
Horizontal Valid
tHA
800
tCLK
