SoCKit User Manual
39
www.terasic.com
December 1, 2015
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The DDR3 devices that are connected to the HPS are the exact same devices connected to the
FPGA in capacity (1GB) and data-width (32-bit), comprised of two x16 devices with a single
address/command bus. This interface connects to dedicate Hard Memory Controller for HPS I/O
banks and the target speed is 400 MHz.
Table 3-25
lists DDR3 pin assignments, I/O standards and
descriptions with Cyclone V SoC FPGA.
Table 3-25 Pin Assignments for DDR3 Memory
Signal Name
FPGA Pin No. Description
I/O Standard
HPS_DDR3_A[0]
PIN_F26
HPS DDR3 Address[0]
SSTL-15 Class I
HPS_DDR3_A[1]
PIN_G30
HPS DDR3 Address[1]
SSTL-15 Class I
HPS_DDR3_A[2]
PIN_F28
HPS DDR3 Address[2]
SSTL-15 Class I
HPS_DDR3_A[3]
PIN_F30
HPS DDR3 Address[3]
SSTL-15 Class I
HPS_DDR3_A[4]
PIN_J25
HPS DDR3 Address[4]
SSTL-15 Class I
HPS_DDR3_A[5]
PIN_J27
HPS DDR3 Address[5]
SSTL-15 Class I
HPS_DDR3_A[6]
PIN_F29
HPS DDR3 Address[6]
SSTL-15 Class I
HPS_DDR3_A[7] PIN_E28 HPS
DDR3 Address[7]
SSTL-15 Class I
HPS_DDR3_A[8]
PIN_H27
HPS DDR3 Address[8]
SSTL-15 Class I
HPS_DDR3_A[9]
PIN_G26
HPS DDR3 Address[9]
SSTL-15 Class I
HPS_DDR3_A[10]
PIN_D29
HPS DDR3 Address[10]
SSTL-15 Class I
HPS_DDR3_A[11]
PIN_C30
HPS DDR3 Address[11]
SSTL-15 Class I
HPS_DDR3_A[12]
PIN_B30
HPS DDR3 Address[12]
SSTL-15 Class I
HPS_DDR3_A[13]
PIN_C29
HPS DDR3 Address[13]
SSTL-15 Class I
HPS_DDR3_A[14]
PIN_H25
HPS DDR3 Address[14]
SSTL-15 Class I
HPS_DDR3_BA[0] PIN_E29
HPS
DDR3
Bank Address[0]
SSTL-15 Class I
HPS_DDR3_BA[1]
PIN_J24
HPS DDR3 Bank Address[1]
SSTL-15 Class I
HPS_DDR3_BA[2]
PIN_J23
HPS DDR3 Bank Address[2]
SSTL-15 Class I
HPS_DDR3_CAS_n
PIN_E27
DDR3 Column Address Strobe
SSTL-15 Class I
HPS_DDR3_CKE
PIN_L29
HPS DDR3 Clock Enable
SSTL-15 Class I
HPS_DDR3_CK_n PIN_L23
HPS
DDR3
Clock
Differential 1.5-V SSTL Class I
HPS_DDR3_CK_p PIN_M23
HPS
DDR3
Clock p
Differential 1.5-V SSTL Class I
HPS_DDR3_CS_n
PIN_H24
HPS DDR3 Chip Select
SSTL-15 Class I
HPS_DDR3_DM[0]
PIN_K28
HPS DDR3 Data Mask[0]
SSTL-15 Class I
HPS_DDR3_DM[1]
PIN_M28
HPS DDR3 Data Mask[1]
SSTL-15 Class I
HPS_DDR3_DM[2]
PIN_R28
HPS DDR3 Data Mask[2]
SSTL-15 Class I
HPS_DDR3_DM[3]
PIN_W30
HPS DDR3 Data Mask[3]
SSTL-15 Class I
HPS_DDR3_DQ[0]
PIN_K23
HPS DDR3 Data[0]
SSTL-15 Class I
HPS_DDR3_DQ[1]
PIN_K22
HPS DDR3 Data[1]
SSTL-15 Class I
HPS_DDR3_DQ[2]
PIN_H30
HPS DDR3 Data[2]
SSTL-15 Class I
HPS_DDR3_DQ[3]
PIN_G28
HPS DDR3 Data[3]
SSTL-15 Class I
HPS_DDR3_DQ[4]
PIN_L25
HPS DDR3 Data[4]
SSTL-15 Class I
HPS_DDR3_DQ[5]
PIN_L24
HPS DDR3 Data[5]
SSTL-15 Class I
