SDI-FMC User Manual
48
April 22, 2019
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Project Source Code
The source code of this Quartus project for the loopback demo with the HAN board is available in
the “Demonstrations\HAN_12G_SDI” folder from the SDI-FMC System CD.
4.6
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The reference clock of SDI IP comes from the Si5344 clock generator chip on the SDI-FMC.
Terasic provides a Si5344 configure IP for developers to configure Si5344 to generate the required
reference clock. The IP can be used to configure Si5344 to generate the following clock setting:
⚫
OUT0: 297.0 MHz clock which is connected to GBTCLK_M2C_P0
⚫
OUT1: 22.5792 MHz clock which is connect co MUX DS250
⚫
OUT2: 254 MHz clock which is connected to SMA connector
⚫
OUT3: 297.0/1.001 MHz clock which is connect to GBTCLK_M2C_P1
The OUT0 and the OUT3 clock can be used as a reference clock of SDI IP. The IP also allow users
to select the 27MHz clock source for Si5344 through the 1 pin interface
MODE
.
When the MODE is set to low, the 27MHz comes from the LMH1938 chip is used. When the MOD
E is set to lit, the 27MHz comes from FPGA mainboard is used. In this case, developers need to
generate the required 27MHz clock. The IP is defined below.
