Terasic HDMI-FMC, Руководство пользователя

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HDMI-FMC_User_Manual www.terasic.com
August 6, 2019
0x19 is written.
9
Set up
Interrupt Service
0x3C
host
→
TPI: Enable hardware interrupts to be serviced
(TPI 0x3C)
→
Important Note: For TPI operation, always write device address 0x72, register offset 0xC7 = 0x00 as the first
step after hardware reset.
Step 1 above is mandatory to allow operation of the TPI register set on HDMI transmitters. If the write is not done
as the first register write, the transmitter will revert to Compatible Mode register set operation; the TPI registers will
not be accessible.
After powering up the transmitter, the host should write the following sequence to enable source termination.
a) Write 0xBC=0x01 // Internal page 0
b) Write 0xBD=0x82 // Indexed register 82
c) Read 0xBE // Read current value
d) Modify bit[0] = 1 // Enable source termination
e) Write 0xBE // Write back modified value
SiI9136-3 Tx only. This device requires the TMDS PLL bandwidth control to be set for 0.75x operation. After
powering up the transmitter, the host should write the following sequence to set the bandwidth control for 0.75x
operation.
a) Write 0xBC=0x01 // Internal page 0
b) Write 0xBD=0x80 // Indexed register 80
c) Write 0xBE=0x24 // Write bandwidth control
◼
Transmitter Programming Interface (TPI) Register
TPI provides a programming interface that operates at a higher hardware level than traditional register
file interfaces. The TPI register groups Table 3-1 handle all normal chip operations in a concise
format.
Table 3-1 Register Group Summary
Group
Function
Register
Addresses
Register Name
What Firmware Does with these
Registers
Identification 0x1B–1D Identification Identifies the chip and version of TPI