UL865-N3G Hardware User Guide
1VV0301177 Rev 2– 2015-04-20
Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights
Reserved.
Page 42 of 70
Mod. 0805 2011-07 Rev.2
10.
SPI Port
The UL865-N3G V2 Module is provided by one SPI interface.
The SPI interface defines two handshake lines for flow control and mutual wake-up of the
modem and the Application Processor: SRDY (slave ready) and MRDY (master ready).
The AP has the master role, that is, it supplies the clock.
The following table is listing the available signals:
PAD
Signal
I/O
Function
Type
Comment
44
SPI_MISO
O
SPI_MISO
CMOS 1.8V
Shared with RX_AUX
45
SPI_MOSI
I
SPI_MOSI
CMOS 1.8V
28
SPI_SRDY
I/O
SPI_SRDY
CMOS 1.8V
Shared with GPIO_06 / ALARM /
27
SPI_MRDY
I/O
SPI_MRDY
CMOS 1.8V
Shared with GPIO_07 / BUZZER /
25
SPI_CLK
I/O
SPI_CLK
CMOS 1.8V
CMOS 1.8V
NOTE:
Due to the shared functions, when the SPI port is used, it is not possible to use the Auxiliary
UART, GPIO_06, GPIO_07 and related alternate functions.
10.5.
SPI Connections
