S42M Hardware User Guide
1VV0301379 Rev. 4
Page
16
of
48
2018-11-28
4.3.2.
Serial Interface with UICP
A substantially saving of power during idle phases can be achieved (see 6.5.1) when the
UICP protocol is used (refer to [2]). This protocol should be implemented on the host side
as well. Signals IUR-IN# and IUR-OUT# should be connected to the host and may be
mapped to DSR and DTR, if an RS232-style (DTE-type) interface is used (see Figure 7).
2
S42M
GND
MAX3241
14
+3V3
22
23
2
3
7
8
4
6
1
9
TXD
RXD
RTS#
CTS#
IUR-OUT#
IUR-IN#
TXD
RXD
RTS
CTS
DTR
DSR
DCD
RI
RS232
DSUB9 (male)
9
4
10
5
11
6
7
8
19
13
18
12
17
16
15
F-4
D-2
D-7
F-3
B-4
D-5
UART_TXD
UART_RXD
UART_RTS#
UART_CTS#
IUR-OUT#
IUR-IN#
SHDN#
EN#
100n
100n
28
24
1
+3V3
100n 100n 100n
26
3
27
25
V+
VCC
V -
GND
C2+
C2-
C1+
C1-
220R
220R
220R
220R
220R
220R
5
SigGND
can be left open
VSUP
+3V3
D
T
E
s
ty
le
c
o
n
n
e
c
to
r
p
in
o
u
t
Figure 7: S42M Example Serial Interface (RS-232) Supporting UICP
If I/O line availability at the host side is extremely tight, 2 I/O lines could be saved by using
the following scheme. This would come at the cost of
•
The host is not allowed to enter sleep mode.
•
The host must accept incoming data at all times and is not able to stop the
Sx sending data. This may be difficult to control for all scenarios and
adds the risk that data gets lost.
•
The host doesn’t implement UICP, but wake-up BT via GPIO.
UART-TXD
GND
UART-RXD
IUC_IN# / CTS#
UART-RXD
UART-TXD
B
lu
eM
o
d
+
Sx
H
o
st
RTS#
CTS#
IUC_OUT# / RTS#
IUR_OUT#
IUR_IN#
BM+Sx-WKUP
Figure 8: Five Wire Interface supporting UICP
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