Teletype 43K001/AAA, Руководство по ремонту

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525, 4-2
2. KEYSWITCH LOGIG
On each scan, the keyswitch logic transmits a
SYNC pulse to establish synchronization. The
keyswitch logic will then send a series of DE
pulses, one pulse per every 12 clock cycles.
A test signal, End of Scan (EOS/Alarm) is
provided for use as a timing reference. End of
Scan is active twenty-four 01 periods after the
Sync pulse.
When a key switch has been sensed as "depressed",
the keyswitch logic will determine if it is to be
sent as a character or is to modify the code of
another keyswitch (ie, CAPS LOCK, SHIFT,
CTRL or REPT). If the code is to be sent, it
will appear as mark-space data on the serial sent
data lead. The mark (high) level of Send Data
and Repeat Mode (RPMD) is limited to +5 V
by CR2, CR3, CR4 and R7 (F7). The code
consists of 11 bits: One start bit, 8 code bits, one
parity bit and one stop bit. One bit time
=
143
milliseconds.
3.
CLOCK GENERATION AND DRIVERS
The 560 KHz clock from pin 12 of P107 (C1) is
divided by 5 by MLB3, R28 R29, Cll and
C12 delay appropriate edges of the 110 KHz
signal and are recombined
MLB1 and MLB2 to
produce nonoverlapping and
�
predrive
signals at pin 11 of MLB1 and MLB2. The non­
overlap time is .3 microseconds minimum to
1.2 microseconds maximum for both nonover­
laps.
The predrive signals are coupled to MLA4 by
C6 and C7. R14 and R15 limit the current
levels. CR8, R34 and CR9, R35 insure a proper
voltage swing for the clock driver. Clock driver
MLA4 is a high voltage dual inverter. R16 and
R17 prevent inductive ringing of the fast
transitions on �1 and �2.
50K122 KEYBOARD
1.
KEYSWITCH LOGIC
Each capacitive keyswitch in the matrix array is
connected to a sense input on MLBl. Keyswitch
validation is accomplished by comparison of the
drive pulse voltage, coupled through the matrix
to the sense inputs, with the fixed voltage of an
analog comparator internal to MLBl. The
comparator then presents key down information
to the validation logic which is also internal to
MLB1.
When a keyswitch has been validated as depressed,
MLB1 will determine if the code is to be sent as
a character or if it is to modify the code of
another keyswitch (ie, CAPS LOCK, Slj:IFT,
CTRL, or REPT). If the code is to be sent, it
will appear as mark space data on the serial data
lead. This lead (pin 6 at J1) is normally at the
marking level. The marking level output
voltage is greater than 4.5 volts, but less than the
+5 volt supply. The spacing or low level output
voltage is greater then 0 volts, but less than
0.5 volts. Output impedance for both serial
data and repeat mode shall be less than 5K ohms
in either logic state.
Repeat mode lead is at the low level as long as
the REPEAT key is not depressed. When
depressed, the repeat mode lead of MLB1 goes
to the high level. When released the lead will
return to the low level. If any other keyswitch
is depressed while the REPEAT key is depressed,
the character associated with that keyswitch
will be sent once every 2.3 ms.
The CPS, DUPLEX, PARITY, and PRINTER
TEST keys are normally open switches. When
depressed the corresponding pins in J1 are
connected to ground.
A 560 KHz square wave input from pin 12
of J1 is divided down to create
all
the timing
signals needed
to
scan the matrix. Each key
requires 28.6 ms to interrogate, and the entire
75 keys are scanned each 2.15 ms.
2. POWER ON RESET AND POWER
DISTRIBUTION
At power turn on approximately 0.5 seconds
of power on reset delay is provided by resistor
R2 and capacitor C4. During power on reset
the serial data lead is held marking and the
repeat mode is held off. The keyswitch array
scanning is suppressed during power on reset.
The
reset function is provided by the
substrate diode in MLBl.
Zener diode CR1 and resistor R1 provide a
+5 volt supply for MLB1.
Capacitors C1 and C2 provide power supply
decoupling.
43K001 RO KEYBOARD
1.
SEND DATA OUTPUT
Depressing the RESET key or releasing the
PRINTER TEST key causes the keyboard to
serially transmit a four character sequence to