U
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ANUAL
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Web
Direction
First
Pixel
Readout
Direction
Forward/reverse information has to be set correctly as soon as the Mode “2S”, “4S” or 2SB of the sensor are set :
In these modes, the sensor/Camera need to know what is the real order of the lines for the exposure delays.
The Forward direction is defined as detailed beside
:
Note
: The minimum delay for the Camera to take
in account a change in the ScanDirection value is :
Using CC3 signal :
100ms
.
Using serial command
(*)
:
120ms
(*)
After reception of the Command on the camera side
If the Camera is in
4S
Sensor mode, after changing
of the scanning direction, the 5 first following
triggers will be ignored in order to reinitialize the
“Full Exposure Control” mode. Then the 3 following
lines acquired will be more or less black because in
4S, 4 lines are required for a complete exposure.
In
2S or 2SB
Sensor modes, no Trigger will be lost
after the change of scanning direction but the first
line acquired will be more or less black as in 2S, 2
lines are required for a complete exposure.
In
1S
,
1SB
or
4SB
modes, nothing is lost an all lines received after the delay are correct.
This positioning takes also in account that the mode “Reverse X” is “Off” (Normal readout direction)
Test Image Selector
(
TestImageSelector
) :
Defines if the data comes from the Sensor or the FPGA (test
Pattern). This command is available in the CommCam “Image Format” section :
Read function : “
r srce
”;
Returned by the camera : “0” if Source from the Sensor and “1 to 5” if test pattern active
Write function : “
w srce
” <value> :
“0” : To switch to CCD sensor image
“1” :
Grey Horizontal Ramp (Fixed) :
See AppendixA
“2” :
White Pattern (Uniform white image : 255 in 8Bits or 4095 in 12bits)
“3” : Grey Pattern (Uniform middle Grey : 128 in 8bits or 2048 in 12 bits)
“4” : Black Pattern (Uniform black : 0 in both 8 and 12 bits)
“5” : Grey vertical Ramp (moving)
The test pattern is generated in the FPGA : It’s used to point out any interface problem with the Frame Grabber.
When any of the Test pattern is enabled, the whole processing chain of the FPGA is disabled.