Teledyne Lecroy PXP500, Руководство пользователя

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Switch Configuration and Connections
Clock Source Diagram
Table 1: 100MHz SSC Internal Clock Configuration
Table 2: Z5 Slot / DUT Slot Clock Source
Table 3: Z5 Slot / DUT Slot Clock Mode Configuration
SEL1 SEL0 Clock downspread amount (%)
Off Off No SSC (Default setting)
Off On -0.1 (1000 ppm)
On Off -0.3 (3000 ppm)
On On -0.5 (5000 ppm)
Z5 Slot External Clock for Z5 Slot comes from Ref Clk In connector
Internal Clock for Z5 Slot comes from Internal Clock (default setting)
DUT Slot External Clock for DUT Slot comes from Ref Clk In connector
Internal Clock for DUT Slot comes from Internal Clock (default setting)
Common Clock for Z5 Slot and DUT Slot are the same (default setting)
Separate (SRIS) Clock for Z5 Slot and the DUT Slot are separate and per source switch
(see Table 2)
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