Teledyne Lecroy PCI Express Gen4 OCP NIC 3.0 Interposer, Руководство пользователя и краткое руководство по началу работы, Страница: 2 / 8

Connections
Perform the following steps to connect the Interposer (see the image below):
1. Set the SW2 DIP switch to the desired positions to set the Host configuration according to the table below
(see
Section “4” on page iii ).
2. Slide the Gen4 OCP NIC 3.0 device into the device bracket and carefully push it into it’s mating connector on the Gen4 OCP NIC 3.0 Interposer.
Connect the Summit T416 Analyzer (or other compatible Teledyne LeCroy analyzer) to the interposer using two Gen4 Y cables
(PE021UCA-X).
3. Make sure the interposer is properly latched to the server. See Section “6” on page v .
4. Connect the analyzer to a host computer system using the USB port on the front panel of the Summit analyzer.
5. If not already done, install the PCIe Protocol Analysis software on the host machine.
6. Connect 12V DC using the AC adapter supplied with the interposer. Make sure that the AC adapter is powered on.
7. Power on the analyzer.
8. Launch the PCIe Protocol Analysis application, setup the appropriate recording options and start a recording. For more information see the Summit
T4 PCI Express Multi-Lane Protocol Analyzer User Manual, Gen4 OCP NIC 3.0 Interposer Configurations.
9. Install the Interposer into the host system connector.
10. Power on the host machine.
11. Use the PCIe Protocol Analysis application to monitor, record and view PCI Express traffic passing through the Gen4 OCP NIC 3.0 Interposer.
Note : For step 9, if testing for hot plug, run recording first from the PCIe Protocol Analysis software then install the interposer into the host system connector.
Make sure the interposer is properly latched to the server. See Section 6.
Connecting the PCI Express Gen4 OCP NIC 3.0 Interposer to a Summit T416 Analyzer
Gen4 Y Cable
Upstream
PE021UCA-X
Summit T416 Analyzer
OCP
NIC 3.0 Hos
t Slot
12V DC from
adapter supplied
External Clock
Inputs MMCX
(Optional Connection)
Device Under Test
(OCP NIC 3.0)
Lane Activity LEDs
SW2: Clock
Configuration
selection
SW1: DUT Power
Status LEDs
SW4: Link Width
selection switch
SW3: NC-SI PHY
Reset
Part of Bottom Cover
which holds DUT
Long Channel
Gen4 Y Cable
Downstream
PE021UCA-X
A
A
B
B
J8: Sideband
Signal header
A C
B
D
To upstream connection
in the analyzer
3