Tektronix DSA8300, Руководство по обслуживанию

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Theory of Operation
All module calibration signals are derived from a 2.5 V precision voltage reference
internal to the sampling module. Settings derived from this reference are stored in
a nonvolatile EEPROM in the sampling module, although the responsibility for
the execution of these settings is with the mainframe.
When used in the acquisition mode (that is, with the TDR step generator turned
off) each channel functions as a normal sampling input. In the TDR mode, a fast
rise time step is generated internally for each channel and applied to the input
signal path for that channel. The acquisition part of the TDR/sampling module
remains functional for monitoring the primary step and its re
fl ected components.
The sampling module provides two self-contained TDR channels. The polarity
of the output step can be selected independently for each channel. This allows
differential or common mode testing of two coupled lines as well as independent
testing of isolated lines.
Optical Sampling Modules
80CXX and 80CXX-CR optical modules share the same mechanical package and
are built with a common circuit board. Different functionality within the modules
(current and future modules) is achieved by installing different O/E modules,
fi lters and clock recovery boards along with setting the sampler bandwidth as
demanded. The key features supported in the module are:
A one channel, low noise, adjustable bandwidth sampler allowing multiple
bandwidth settings for optimizing noise versus bandwidth demands.
An ampli fi ed or nonampli fi ed O/E converter.
Support for internal RF switches in the signal path with a straight-through
path and three hardware- fi ltered reference receiver paths between the O/E
converter and the sampler.
An average optical power meter.
Integral clock recovery option with internal coaxial connection to the
mainframe trigger, front panel clock and data output (not all have data).
Communication with the mainframe for identi fi cation, control and
calibration/compensation storage.
The "system response" depends on all of the components in the signal path from
the front panel to the sampler. Bandwidth and reference receiver responses are
calibrated at the factory with a sub-picosecond optical impulse applied to the
front panel connector or with an optical heterodyne system. This ensures that all
components are included, but also means that components cannot be replaced
without performing calibration.
Compensation performs a DC transfer curve characterization for each
bandwidth/reference receiver setting. The curve data is stored in the module
EEPROM and used to generate a look-up table in the mainframe. This data
corrects for linearity, gain and offset errors in the sampler.
2–6 DSA8300 Digital Serial Analyzer and Modules Service Manual