Tektronix 80A07, Руководство пользователя

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80A07 Clock Recovery User Manual
1
Getting Started
This section contains information on key features of your instrument, installing
your instrument, and getting acquainted with the controls.
Clock Recovery
Many communication standards now specify that jitter testing must be carried
out using a reference clock that has been derived from the data signal. Typical
phase lock loop (PLL) characteristics are specified in terms of the --3 dB
bandwidth of the recovery loop, the rate of rolloff of the frequency response, and
the degree of response peaking allowable.
The 80A07 measures and displays the PLL frequency response from 100 kHz to
12 MHz. The 80A07 allows full control of parameters including loop bandwidth
(LBW), peaking/damping and rolloff.
Design and test engineers can now find and lock onto signals of undefined or
unknown data rates. The engineer can recover full-rate clocks, including spread
spectrum clocks, for signals at data rates from 100 Mb/s to 12.5 Gb/s. The
engineer has full control of key parameters for variable-loop bandwidth,
peaking/damping and first and second order rolloffs, optimizing jitter tracking.
Many test standards require the use of a Golden PLL (phase lock loop.) To
assure repeatability, most serial data compliance test standards specify the PLL
characteristics for jitter measurement. Each standard provides an optimum LBW
setting for clock recovery, often called the Golden PLL.
The 80A07 has been designed to provide users with flexibility and accuracy in
compliance measurements. It is ideal for optical test applications, like 4x/8x
Fibre Channel and 10G Ethernet standards, where the signal under test must be
split off and converted from optical to electrical before being fed into the clock
recovery data input. The 80A07 recovers a full-rate clock up to 12.5 Gb/s, an
important requirement for testing XFP and other 10 Gb/s MSA modules.
Golden PLL
Recover Clocks for
Optical Storage,
Enterprise and Telecom
Testing