Tekram Technology P5T30-B4, Руководство пользователя

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MAINBOARD BIOS SETUP MAINBOARD BIOS SETUP
P5T30-B4 User’s Manual
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C8000-DFFFF Shadow - These options control the location of the contents of the 16KB
expansion card ROMs beginning at the specified memory location. If no adapter ROM is
using the named ROM area, this area is made available to the local bus. Shadowing a ROM
reduces the memory available between 640KB and 1024KB by the amount used for this
purpose. The settings are
Enabled or Disabled .
CHIPSET FEATURES SETUP
This setup menu contains advanced configuration options relating to the mainboard chipset.
These options are rarely changed by the user.
Auto Configuration : Enabled ** System Hardware Monitor **
CPU Overheat Alarm (> 65
°
C)
: Enabled
DRAM Timing : 70ns CPU Fan Malfunction Alarm : Enabled
DRAM Leadoff Timing : 10/6/4 System 5V Alarm (< 4.7V) : Enabled
DRAM Read Burst (EDO/FP) : x333/x444
DRAM Write Burst Timing : x333
Fast EDO Lead Off : Enabled
Refresh RAS# Assertion : 5 Clks
SDRAM (CAS Lat/RAS-to-CAS) : 3/3
SDRAM Speculative Read : Disabled
System BIOS Cacheable : Disabled
Video BIOS Cacheable : Enabled
8 Bit I/O Recovery Time : 1
16 Bit I/O Recovery Time : 1
ESC : Quit
↑ ↓ → ←
: Select Item
Memory Hole At 15M-16M : Disabled F1 : Help PU/PD/+/- : Modify
PCI 2.1 Compliance : Disabled F5 : Old Values (Shift) F2 : Color
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
Auto Configuration - When Enabled , pre-defined values for 60ns DRAM, Cache, Timings,
etc. are set according to the CPU type & system clock. Enabled is the recommended setting.
These settings are only editable when Auto Configuration is Disabled .
Note: The first chipset settings deal with CPU access to dynamic random access memory
(DRAM). The default timings have been carefully chosen and should only be altered if data
is being lost. Such a scenario might occur if your system had mixed speed DRAM chips
installed. Here, greater delays may be required to preserve the integrity of the data held in
the slower memory chips.
DRAM Timing - DRAM timing is controlled by the DRAM timing registers. The timings
programmed into this register are dependent on the system design. 60ns is the fastest rate.
The 70ns timing is slower and may be required in certain system designs to support loose
layouts or slower memory.