TechNexion EDM1-IMX6PLUS, Руководство по оборудованию

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EDM1-IMX6PLUS HARDWARE MANUAL
– VER 1.00 – NOV 16 2016
Page 55 of 83
3.13. Serial Peripheral Interface (SPI)
The EDM1-IMX6PLUS features two Enhanced Configurable SPI ports, which are derived from the i.MX6
processor, integrated ECSPI IPs.
The following main features are supported:

Full-duplex synchronous serial interface

Master/Slave configurable

Transfer continuation function allows unlimited length data transfers

32-bit wide by 64-entry FIFO for both transmit and receive data

32-bit wide by 16-entry FIFO for HT message data

Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable Direct Memory
Access (DMA) support
For additional details, please refer to the “Enhanced Configurable SPI (ECSPI)” chapter of the “i.MX6
Reference Manual”.
Table 30 - Primary SPI Channel Signal Description
EDM
PIN
i.MX6
BALL PAD NAME Signal V I/O Description
219 J23 EIM_CS1 ECSPI2_MOSI 3V3 O
Serial Peripheral Interface
primary channel master output
slave input signal
221 J24 EIM_OE ECSPI2_MISO 3V3 I
Serial Peripheral Interface
primary channel master input
slave output signal
223 H24 EIM_CS0 ECSPI2_SCLK 3V3 O
Serial Peripheral Interface
primary channel clock signal
225 K20 EIM_RW ECSPI2_SS0 3V3 O
Serial Peripheral Interface
primary channel Chip Select 0
signal
227 K22 EIM_LBA ECSPI2_SS1 3V3 O
Serial Peripheral Interface
primary channel Chip Select 1
signal. Do not use if only 1
SPI device is used