Teac PL-D200V, Руководство по обслуживанию

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99
Name Number I/O Definition
MCLK 39 I/O Audio master clock for audio DAC.
TBCK 40 O Audio transmit bit clock.
SPDIF 41 O S/PDIF output.
SEL_PLL3 I Clock source select.
NC 42, 48 No connect pins. Leave open.
RSD 45 I Audio receive serial data.
RWS 46 I Audio receive frame sync.
RBCK 47 I Audio receive bit clock.
XIN 49 I Crystal input.
XOUT 50 O Crystal output.
AVEE 51 I Analog power for PLL.
DMA[11:0] 66:61, 58:53 O DRAM address bus [11:0].
DCAS# 69 O DRAM column address strobe.
DOE# 70 O DRAM output enable.
DSCK_EN O DRAM clock enable.
DWE# 71 O DRAM write enable.
DRAS# 72 O DRAM row address strobe.
DMBS0 73 O SDRAM bank select 0.
DMBS1 74 O SDRAM bank select 1.
DB[15:0] 96:93, 90:85, I/O DRAM data bus [15:0].
82:77
DCS[1:0]# 97,100 O SDRAM chip select [1:0].
DQM 101 O Data input/output mask.
DSCK 102 O Output clock to SDRAM.
DCLK 105 I 27 MHz clock input to PLL.
YUV0 O YUV0 pixel output data.
CAMIN2 I Camera input 2.
UDAC O Video DAC output.
106
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
SEL_PLL3 Clock Source
0 Crystal oscillator
1 DCLK input
Mode YDAC UDAC VDAC CDAC
A Y C Composite C
B Y Composite Composite C
C Y U Composite V
D Y U C V