PYH200 Manual
DC-DC Converter Isolated, 200W, ½ Brick, PCB Mount
21. S
YNCHRONIZING THE
S
WITCHING
F
REQUENCY
The PYH200 can be synchronized to an external clock by applying a
pulse to the sync pin (3). The external clock frequency must be between
530KHz and 630KHz, which is slightly above the regular switching
frequency. If the external clock frequency is less than the switching
frequency, the PYH200 will ignore the synchronizing pulses. The
synchronization pulse width must have a length of minimum 90nS. The
sync pin (3) must be protected by a 5.6V zener diode. The amplitude of the external clock signal must be
between 3.5V and 4.5V.
3 Sync
6 -Vin
1 +Vin
PYH200
+
+
5 Bus
Pulse
-Vin
+Vin
D1
C1
C4
C1: 100uF/200V ESR<47m
Ω
C4: 240uF (VISHAY 118 AHT series)
D1: 5.6V Zener diode
22. H
OLD
-
UP
T
IME
C
IRCUITRY
The hold time is defined as the time period during which the DC-DC converter output remains active after a
loss of input power. The DC-DC converter itself is not capable of providing a hold time. For this, an external
circuit with a large hold-up (storage) capacitor is required.
D1:
200V/10A
6 -Vin
1 +Vin
PYH200
+
+
5 Bus
-Vin
+Vin
C1
C4
+
C5
D1
R1
Hold-up circuit
R1:
10
Ω
, 3W
C1:
100uF/200V ESR<0.047
Ω
C4:
240uF (VISHAY 118 AHT series)
C5:
see table below, voltage of the capacitor must be larger
than the supply voltage
Sizing the hold-up capacitor C5
Input
Voltage 24Vdc 36Vdc 48Vdc 72Vdc 96Vdc 110Vdc
Hold-up capacitor
(C5) for 10ms
2400µF 2400µF 2400µF 2400µF 820µF 560µF
Hold-up capacitor
(C5) for 30ms
7200µF 7200µF 7200µF 7200µF 2460µF 1680µF
All parameters are typical values specified at nominal input voltage, nominal output load, 25°C ambient and after a 5 minutes run-in time unless
otherwise noted. The information presented in this document is believed to be accurate and reliable and may change without notice.
For additional information, please visit https://product.tdk.com/info/en/products/power/index.html
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DOC-ID: IM-PYH200-2022-05-04