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X7DWN+ User's Manual
Memory Voltage
Select Auto to allow the BIOS to automatically detect memory voltage based on
the SPD table. Select 1.5V to force the system to use 1.5V for lower power fully-
buffered DIMM modules. Select 1.8V to use 1.8V power for onboard memory
modules. Note: Using 1.8V might cause damage to the memory modules that only
support 1.5V power. The options are:
Auto
, 1.5V and 1.8V.
Memory Branch Mode
This option determines how the two memory branches operate. System address
space can either be interleaved between the two branches or Sequential from
one branch to another. Mirror mode allows data correction by maintaining two
copies of data in two branches. Single Channel 0 allows a single DIMM population
during system manufacturing. The options are
Interleave
, Sequential, Mirroring,
and Single Channel 0.
Branch 0 Rank Sparing/Branch 1 Rank Sparing
Select
Enable
to enable the function of memory sparing for Memory Bus Branch
0 or Branch 1. The options are Enabled and
Disabled
.
Branch 0 Rank Interleaving/Branch 1 Rank Interleaving
Select enable to enable Interleaved Memory for Memory Bus Branch 0 Rank or
Branch 1 Rank. The options for Memory Interleaving are 1:1, 2:1 and
4:1
.
Enhanced x8 Detection
Select
Enabled
to enable Enhanced x8 DRAM UC Error Detection. The options
are Disabled and
Enabled
.
Demand Scrub
Scrubbing is a process that allows the North Bridge to correct correctable memory
errors found on an FBD memory module. When the CPU or I/O issues a demand-
read command, and the read data from memory turns out to be a correctable ECC,
it is corrected and sent to the original source. Memory is updated as well. Select
Enabled to use Demand Scrubbing for ECC memory correction. The options are
Enabled
and Disabled.
High Temperature DRAM Operation
When set to
Enabled, the BIOS will refer to the SPD table to set the maximum
DRAM temperature. If disabled, the BIOS will set the maximum DRAM temperature
based on a predefi ned value. The options are Enabled and
Disabled
.
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