Chapter 2: Installation
2-27
Y2
JT
PM
MH
8
MH7
MH
5
MH
3
MH
2
MH1
MH
9
JPI2
C
SPKR
1
JSPK
FAN1
FAN2
FAN3
FA
N4
T-
SGPIO2
T-
SGPIO1
JF1
JWR4
JWR3
JWF1
JP3
J15
DIMM6
DIMM3
DIMM2
DIMM5
DIMM1
DIMM4
J30
J29
LE
5
SW1
COM1
J5
B1
J1
4
J13
J2
4
JBT1
JL1
JI2C1
JI2C2
LE
3
LE4
LE
7
JPEN1
JLED
JPT1
JPB
JPL1
JPL2
JPG
1
J1
8
U2
BAR C
ODE
5V GND GND
JWOR1:W
ake on Ring
JSPK
:B
uz
ze
r/
Sp
ea
ke
r
FF
COMPACT FLASH POWER
JWF1:
IPMI LAN
USB/0/1
USB/2/3
DIMM2C
DIMM1C
1-2:ENABLE 2-3:DISABLE
JPL2:LAN
2
JPL1:LAN
1
2-3:DISABLE
1-2:ENABLE
JPB:BMC
JPI2C:PWR I2C
DDR3 1066/1333 UDIMM/RDIMM requires
VGA
USB4
JBT1:CMOS CLEA
R
JPT1:TP
M
LAN2
JL
1
LAN1
JPUSB1:B/P USB
W
AKE UP
1-2:ENABLE 2-3:DISABLE
DIMM2B
DIMM2A
USB 10/11
JI2C1/JI2C
2
SLOT1 PCI-E X16 GEN2
2-3:Disable
1-2:Enable
CP
U
JLED:
Po
w
er
L
ED
OF
F:
Disabl
e
ON:Enable
2-3:Disabl
e
1-2:Enable
REV
:1.00
X8SIT
-F
DESIGNED IN US
A
2-3:DISABLE
1-2:ENABLE
:CHASSIS INTRUSION
JF
1
ON
LED
LE
D
PW
R
HDD
NIC
1
NIC
2
OH/
X
RST
PW
R
I-SATA3
I-SATA4
I-SATA2
I-SATA1
I-SATA0
I-SATA5
DIMM1B
DIMM1A
JPG1: VGA
JPUSB
1
(Image rotated -90 degrees)
Serial_Link-SGPIO
Pin Definitions
Pin# Definition
Pin Definition
2
NC
1
NC
4
Data Out
3
Ground
6
Ground
5
Load
8
NC
7
Clock
T-SGPIO 0/1 Headers
Two T-SGPIO (Serial-Link General Pur-
pose Input/Output) headers are located
near the SATA connectors on the moth-
erboard. These headers are used to
communicate with the enclosure manage-
ment chip in the system. See the table on
the right for pin definitions. Refer to the
board layout below for the locations of
the headers.
NC: No Connections
A. T-SGPIO 1
B. T-SGPIO 2
C. CF/DOM Power
C
A
B
Compact Flash/DOM PWR Connector
A Compact Flash/Disk On Module (DOM)
Power Connector is located at JWF1. This
connector is used to provide power to auxil-
liary flash memory media that is attached to
the SATA port. Refer to the board layout
below for the location.
Compact Flash Card PWR
Connector
Pin Definition
1
Vcc
2
GND
3
GND
Содержание Supero X8SIT-F
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