Supero Supero PDSMA, Руководство пользователя

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Chapter 1: Introduction
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1-2 Chipset Overview
Intel’s Mukilteo (E7230) chipset, designed for use with the Pentium 4/Pendium D
Processor in the LGA 775 Land Grid Array Package, is comprised of two primary
components: the Memory Controller Hub (MCH) and the I/O Controller Hub (ICH7R).
The PDSMA provides the performance and feature-set required for the high-end
server and the UP workstation market.
Memory Controller Hub (MCH)
The function of the MCH is to manage the data fl ow between four interfaces: the
CPU interface, the DDR2 System Memory Interface, the PCI Express Interface, and
the Direct Media Interface (DMI). The MCH is optimized for the Pentium 4/Pentium
D processor in the 90nm process in the LGA775 Land Grid Array Package. It sup-
ports one or two channels of DDR2 SDRAM.
The I/O Controller (ICH7R) provides the data buffering and interface arbitration re-
quired for the system to operate effi ciently. It also provides the bandwidth needed
for the system to maintain its peak performance. The Direct Media Interface (DMI)
provides the connection between the MCH and the ICH7R. The ICH7R supports
multiple PCI-Express slots, four Serial ATA ports, six USB 2.0 ports and two IDE
devices. In addition, the ICH7R offers the Intel Matrix Storage Technology which
provides various RAID options for data protection and rapid data access. It also
supports the next generation of client management in conjunction with the next
generation Gigabit Ethernet controller.
Intel ICH7R System Features
The I/O Controller Hub provides the I/O subsystem with access to the rest of the
system. Functions and capabilities include:
*Advanced Confi guration and Power Interface, Version 2.0 (ACPI)
*Intel IIO External Design Specifi cation (EDS)
*Mukilteo Memory Controller Hub (MCH) External Design Specifi cation (EDS)
*Intel I/O Controller Hub 7 (ICH7R) Thermal Design Guideline
*Low Pin Count (LPC) Interface