Supero H8QM3-2+, Руководство пользователя

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Chapter 1: Introduction
1-9
1-4 Chipset Overview
The H8QM3-2+/H8QMi-2+ serverboard is based on the nVidia MCP55 Pro chipset.
The MCP55 Pro functions as Media and Communications Processor (MCP). An
NEC uPD720404 chip is also included as a bridge for the GB LAN ports. Note that
the controllers for the system memory are integrated directly into the AMD CPUs.
MCP55 Pro Media and Communications Processor
The MCP55 Pro is a single-chip, high-performance HyperTransport peripheral con-
troller. It includes a 28-lane PCI Express interface, an AMD Opteron 16-bit Hyper
Transport interface link, a six-port (3 Gb/s) Serial ATA interface, an ATA133 bus
master interface and a USB 2.0 interface. This hub connects directly to CPU1.
NEC uPD720404
This I/O bridge chip provides one PCI-Express x4 upstream port and two PCI-X
domains. Each bridge supports PCI masters that include clock, request and grant
signals. This hub links the MCP55 with the Gb LAN ports.
HyperTransport Technology
HyperTransport technology is a high-speed, low latency point to point link that was
designed to increase the communication speed by a factor of up to 48x between
integrated circuits. This is done partly by reducing the number of buses in the
chipset to reduce bottlenecks and by enabling a more effi cient use of memory
in multi-processor systems. The end result is a signifi cant increase in bandwidth
within the chipset.