Chapter 1: Introduction
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Introduction
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Chipset Overview
Built upon the functionality and the capability of the 7520 Lindenhurst
chipset, the X6DHP-8G motherboard provides the performance and feature
set required for dual processor-based servers, with configuration options
optimized for communications, presentation, storage, computation or data-
base applications. The Intel E7520 (Lindenhurst) chipset consists of the
following components: the Lindenhurst Memory Controller Hub (MCH), the
ICH5R I/O Controller Hub, and the Intel PCI-X Hub (PXH).
The E7520 MCH supports single or dual Xeon EMT64 (Nocona) processors
with Front Side Bus speeds of 800 MHz. Its memory controller provides
direct connection to two channels of registered DDR266, DDR333 with a
marched system bus address and data bandwidths of up to 6.4GB/s. The
E7520 also supports the new PCI high speed serial I/O interface for supe-
rior I/O bandwidth. The MCH interfaces with the ICH5R I/O Controller Hub
(ICH5R) via a dedicated Hub Interface. The PXH provides connection be-
tween a PCI interface and two independent PCI bus interfaces that can be
configured for standard PCI -X 1.0 protocol.
ICH5R System Features
In addition to providing the I/O subsystem with access to the rest of the
system, the ICH5R I/O Controller Hub integrates many I/O functions.
The ICH5R I/O Controller Hub integrates: 2-channel Ultra ATA/100 Bus Mas-
ter IDE Controller, two Serial ATA (SATA) Host w/RAID0, RAID1 support,
SMBus 2.0 Controller, LPC/Flash BIOS Interface, PCI 2.2 Interface and Sys-
tem Management Controller.
(*Notes: The CPU FSB speed is set at 800 MHz by the Manufacturer.
Please do not change the CPU FSB setting.)
