Supermicro X12SCV-W, Руководство пользователя

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Super X12SCV-W User's Manual
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64-bit
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EIST Technology
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CPU C3 state
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CPU C6 state
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CPU C7 state
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CPU C8 state
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CPU C9 state
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CPU C10 state
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L1 Data Cache
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L1 Instruction Cache
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L2 Cache
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L3 Cache
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L4 Cache
C6DRAM
Use this feature to enable or disable the moving of DRAM contents to PRM memory when
the CPU is in the C6 state. The options are
Disabled and Enabled.
Hardware Prefetcher (Available when supported by the CPU)
If set to Enable, the hardware prefetcher will prefetch streams of data and instructions from
the main memory to the L2 cache to improve CPU performance. The options are Disabled
and
Enabled .
Adjacent Cache Line Prefetch (Available when supported by the CPU)
The CPU prefetches the cache line for 64 bytes if this feature is set to Disabled. The CPU
prefetches both cache lines for 128 bytes as comprised if this feature is set to Enable. The
options are Disabled and
Enabled .
Intel (VMX) Virtualization Technology
Use this feature to enable the Vanderpool Technology. This technology allows the system to
run several operating systems simultaneously. The options are Disabled and
Enabled
.