
49
Chapter 2: Installation
General Purpose I/O Header
The JGP1 (General Purpose Input/Output) header is a general purpose I/O expander on a
pin header via the SMBus. Each pin can be configured to be an input pin or output pin in
2.54mm pitch. The GPIO is controlled via the PCA9554APW 8-bit GPIO expansion from PCH
SMBus. The base address is 0xEFA0. The expander slave address is 0x70 for WRITE and
0x71 for READ. See the table below for pin definitions.
JGP1 Header
Pin Definitions
Pin#
Definition
1
+5V
2
GP0
3
GP1
4
GP2
5
GP3
6
GP4
7
GP5
8
GP6
9
GP7
10
Ground
+
X12SCQ
REV:1.00
BAR C
ODE
DESIGNED IN USA
Intel
Q470E
BIOS
LICENSE
M
AC C
ODE
JGP1
DIMMA1
DIMMB1
DIMMA2
DIMMB2
COM12
COM34
MH12
MH11
MH9
JPW2
SP1
JSTBY1
JD1
FAN1
FAN3
FAN4
FAN2
JPT1
JA
T1
JWD1
JLED1
JPL2
JPAC1
JPW1
JL1
I-SA
TA5
I-SA
TA2
I-SA
TA4
I-SA
TA1
I-SA
TA3
I-SA
TA0
JF1
JBT1
JSD1
JTPM1
BT1
CPU F
AN
MH6
MH7
JPME2
MH2
MH1
MH4
MH5
MH3
JPL1
MH8
LED3
PWR_LED
CPU
AUDIO FP
USB4/5
USB6/7(3.2)
SLOT4 PCIe 3.0 x4 SLOT5 PCIe 3.0 x8
SLOT6 PCIe 3.0 x4
ON
PWR
X LED
OH/FF
RST
NIC2 NIC1 HDD
LED
USB10/1
1
(3.2 (10Gb))
LED
PWR
HD AUDIO
SLOT7 PCIe 3.0 x16
UNB NON-ECC DDR4 DIMM REQUIRED
ALWAYS POPULATE BLUE SOCKET FIRST
PCIe M.2-M1
LAN2
USB2/3
USB8/9(3.2)
LAN1
HDMI/DP
DVI-D/VGA
KB/MOUSE
USB0/1
1
1. General Purpose Header