51
Chapter 2: Installation
General Purpose I/O Header (X11SSQ/-V only)
JP7 is a 10-pin general purpose I/O header located near COM1. Each pin can be configured
to be an input pin or output pin in 2.54mm pitch. The GPIO is controlled via the PCA9554
8-bit GPIO expansion from PCH SMBus. The base address is 0xF040(D31:F4). Expander
slave address is 0x70. See the table below for pin definitions.
Chassis Intrusion
A Chassis Intrusion header is located at JL1 on the motherboard. Attach the appropriate cable
from the chassis to the header to inform you when the chassis is opened.
Chassis Intrusion
Pin Definitions
Pins
Definition
1
Intrusion Input
2
Ground
1
10
4
1
1
X11SSQ
REV: 1.01
DESIGNED IN USA
Tested to Comply
With FCC Standards
FOR HOME OR OFFICE USE
BIOS
LICENSE
J23
JPW2
B3
JP7
SP1
LED1
COM3
JSTBY1
JD1
FAN3
FAN4
FAN1
FAN2
JPME2
JWD1
JLED1
JI2C2
JI2C1
JPL2
JPAC1
JPL1
JPW1
JL1
I-SA
TA5
I-SA
TA2
I-SA
TA4
I-SA
TA1
I-SA
TA3
I-SA
TA0
JF1
JBT1
I-SGPIO2
JSD1
JTPM1
COM4
JVR1
I-SGPIO1
LED3
JSMB1
MAC CODE
BAR CODE
COM2
COM1
JAT1
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
AUDIO FP
USB6/7
PCH SLOT4 PCI-E 3.0 X4
PCH SLOT5 PCI-E 3.0 X4
PCH SLOT6 PCI-E 3.0 X1
USB10/11(3.0)
HD AUDIO
CPU SLOT7 PCI-E 3.0 X16
DIMMA2
DIMMA1
DIMMB1
DIMMB2
UNB NON-ECC DDR4 DIMM REQUIRED
ALWAYS POPULATE BLUE SOCKET FIRST
M.2 PCI-E 3.0 X2
LAN2
USB2/3
USB8/9(3.0)
LAN1
HDMI/DP
CPU
DVI-D
CPU FAN
KB/MOUSE
USB0/1
USB4/5
CATERR_LED
J18
1
2
1. General Purpose I/O
Header (X11SSQ/-V only)
2. Chassis Intrusion
General Purpose I/O Header
Pin Definitions
Pin#
Definition
Pin#
Definition
1
+5V Power
6
GPIO4
2
GPIO0
7
GPIO5
3
GPIO1
8
GPIO6
4
GPIO2
9
GPIO7
5
GPIO3
10
GND
General Purpose I/O Pin Layout
1
10
