37
Chapter 2: Installation
SGPIO Header
The S-SGPIO1 (Serial General Purpose Input/Output) header is used to communicate with
the enclosure management chip on the backplane.
SGPIO Header
Pin Definitions
Pin#
Definition
Pin#
Definition
1
NC
2
Data In
3
Reserved 4
DATA Out
5
Load
6
Ground
7
Clock
8
NC
NC = No Connection
IPMI_LAN Port
An IPMI LAN port is located on the I/O back panel to provide network connections. This port
accepts RJ45 type cable.
LAN Port
Pin Definitions
Pin#
Definition
Pin#
Definition
1
P2V5SB 10
NC
2
TD0+
11
DATA Out
3
TD0-
12
Ground
4
TD1+
13
Link 100 LED
(Green, +3V3SB
5
TD1-
14
Link 1000 LED
(Yellow, +3V3SB
6
TD2+
15
Ground
7
TD2-
16
Ground
8
TD3+
17
Ground
9
TD3-
18
Ground
1. SGPIO Header
2. IPMI_LAN Port
X11SSD-F
REV:1.00
DESIGNED IN USA
BAR C
ODE
J4
BT1
SW1
S-SGPIO1
LED2
A
C
LED1
A
C
JSTBY1
JBT1
FAN1
JTPM1
JBR1
JI2C2
JI2C1
J5
JPME2
JPB1
JPG1
JWD1
JVRM2
JVR1
JVRM1
LED3
A
C
DIMMA1
DIMMA2
DIMMB1
DIMMB2
SAS1
SAS0
I-SATA2 I-SATA3
JIPMB1
JSMB1
CPU1 MICRO-LP
PCI-E 3.0 X8
CPU1 SLOT1 PCI-E 3.0 X8
KVM
USB2(3.0)
CPU Socket
LGA1151
IPMI_LAN
UID
JSD1
SATA DOM POWER
SATA DOM+POWER
Intel
C236
1
2
Содержание X11SSD-F
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