4-16
X10QBL-CT/X10QBL User’s Manual
Memory Configuration
This section displays the following Integrated Memory Controller (IMC) informa-
tion.
DDR Speed
Use this feature to force a DDR3 memory module to run at a frequency other
than what is specified in the specification. The options are
Auto
, 1067, 1333,
1600, 1867, and 2133.
ODT (On-Die Termination) Timing Mode
Use this feature to configure the timing mode setting for the ODT
(On-Die Ter-
mination) where the termination resistor for impedance matching in transmission
lines is located inside a chip instead of on a printed circuit board. The options
are
Aggressive Timing
and Conservative Timing.
MxB Rank Sharing Mapping
Use this feature to select the address-mapping setting for memory-rank sharing
to enhance extended multimedia platform performance. The options are
Maxi-
mum Performance
and Maximum Margin.
LRDIMM (Load-Reduction DIMM) Module Delay
When this item is set to Disabled, the MRC (Memory Regulator Controller) will
not use SPD bytes 90-95 for module delay on LRDIMM memory. The options
are
Disabled
and Auto.
Data Scrambling
Select Enabled to enable data scrambling to enhance system performance and
data integrity. The options are Disabled and
Enabled
.
VMSE Lockstep Mode
Select Enabled to support the VMSE Lockstep mode, which will support Lock
step mode for the Intel Scalable Memory Interconnect 2 (Intel SMI 2) controller.
The options are
2:1 Mode
.
HA (Hash Mode) Early Write Post Mode
Select Enable to support memory hash-method-comparison mode when the
system is running at the early stage of POST (Power-On-Self-Test). The options
are is
Enable
and Disable.
Command 2 Data Tuning
Select Enabled to fine-tune electrical command paths from the host system to
the memory-extension buffer (MXB). The options are
Enabled
and Disabled.
