Supermicro SUPERSERVER 8048B-C0R4FT, Руководство пользователя

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Chapter 7: BIOS
7-13

IIO1 Confi guration
No PCIe Port Active ECO
Use this feature to select a workaround setting to implement the engineering-
change order (ECO) on the system when PCI ports are not active. The options
are PCU Squelch exit ignore option, and
Reset the SQ FLOP by CSR option
.

CPU2 SLOT3 PCI-E 3.0 X16/CPU2 SLOT2 PCI-E 3.0 X8/
CPU2 SLOT4 PCI-E 3.0 X8
Use the items below to con fi gure the PCI-E settings for a PCI-E port speci fi ed
by the user.
The following items will display:
•
PCI-E Port Link Status
•
PCI-E Port Link Max
•
PCI-E Port Link Speed
Link Speed
Use this item to select the PCI-E link speed for the PCI-E port speci fi ed by the
user. The options are
Auto
, GEN1 (2.5 GT/s),
GEN2 (5 GT/s)
, and GEN3 (8
GT/s).

IOAT (Intel® IO Acceleration) Confi guration
Enable IOAT
Select Enable to enable Intel I/OAT (I/O Acceleration Technology) support,
which will signi
fi cantly reduce CPU overhead by leveraging CPU architectural
improvements and freeing the system resource for other tasks. The options are
Enable
and Disable.
No Snoop
Select Enable to support no-snoop mode for each CB device. The options are
Disable
and Enable.
Disable TPH (TLP Processing Hint)
.
If this item is set to Enable, TLP Processing Hint will be disabled. The options
are Disable and
Enable
.