SuperServer 5039MD(8/18)-H8TNR User's Manual
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Memory Rank Sparing
Select Enable to enable memory-sparing support for memory ranks to improve memory
performance. The options are
Disable
and Enable.
Correctable Error Threshold
Use this feature to specify the threshold value for correctable memory error logging,
which sets a limit on the maximum number of events that can be logged in the memory
error log at a given time. Select a value between 1-32776. The default setting is
7fff
.
SDDC
Single device data correction (SDDC) organizes data in a single bundle (x4/x8 DRAM).
If any or all the bits become corrupted, corrections occur. The x4 condition is corrected
on all cases. The x8 condition is corrected only if the system is in Lockstep Mode. The
options are
Disable
and Enable.
ADDDC Sparing
Adaptive Double Device Data Correction (ADDDC) Sparing detects when the prede-
termined threshold for correctable errors is reached, copying the contents of the failing
DIMM to spare memory. The failing DIMM or memory rank will then be disabled. The
options are
Disable
and Enable.
Patrol Scrub
Patrol Scrub is a process that allows the CPU to correct correctable memory errors
detected on a memory module and send the correction to the requestor (the original
source). When this item is set to Enable, the IO hub will read and write back one cache
line every 16K cycles if there is no delay caused by internal processing. By using this
method, roughly 64 GB of memory behind the IO hub will be scrubbed every day. The
options are Disable and
Enable
.
Patrol Scrub Interval
This feature allows the user to decide how many hours the system should wait before
the next complete patrol scrub is performed. Use the keyboard to enter a value from
0-24. The default setting is
24
.
IIO Configuration
Socket0 Configuration
IOU0 (II0 PCIe Br1) / IOU1 (II0 PCIe Br2)
This features configure the PCI-E port Bifuraction setting for a PCI-E port specified by
the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and
Auto
.
MCP0 (II0 PCIe Br4) / MCP1 (II0 PCIe Br5)
This features configure the PCI-E port Bifuraction setting for a PCI-E port specified by
the user. The options are x16 and
Auto
.