2-28
X6DHR-TG User's Manual
IDE Connectors
T h e r e a r e n o j u m p e r s t o
configure the onboard IDE#1
and #2 connectors (at J5
and J6, respectively). See
the table on the right for pin
definitions.
Pin Number
Function
1
Reset IDE
3
Host Data 7
5
Host Data 6
7
Host Data 5
9
Host Data 4
11
Host Data 3
13
Host Data 2
15
Host Data 1
17
Host Data 0
19
GND
21
DRQ3
23
I/O W rite-
25
I/O Read-
27
IOCHRDY
29
DACK3-
31
IRQ14
33
Addr 1
35
Addr 0
37
Chip Select 0
39
Activity
Pin Number
Function
2
GND
4
Host Data 8
6
Host Data 9
8
Host Data 10
10
Host Data 11
12
Host Data 12
14
Host Data 13
16
Host Data 14
18
Host Data 15
20
Key
22
GND
24
GND
26
GND
28
BALE
30
GND
32
IOCS16-
34
GND
36
Addr 2
38
Chip Select 1-
40
GND
IDE Connector Pin Definitions
(J5, J6)
IPMI
J 9 i s d e s i g n a t e d a s t h e I P M I
Socket for the Motherboard.
IPMI
IDE1
IDE2
K B
DIMM 4B
Mouse
U S B
0 / 1
COM1
DIMM 4A
DIMM 3B
DIMM 3A
DIMM 2B
DIMM 2A
DIMM 1B
DIMM 1A
GLAN1
GLAN2
VGA
Battery
JPG1
JPL1
RAGE-
X L
GLAN
C T R L
P X H
PCI-X 133 MHz
PCI-X 100 MHz
E 7 5 2 0
(North Bridge)
ICH5R
(South
Bridge)
ZCR RAID
IPMI 2.0
IDE #1
IDE #2
Floppy
WOL
COM2
Fan3
U S B 2 / 3
JBT1
F
P
C
T
R
L
FAN2
F A N 1
20-Pin ATX PW
PW SMB
J L 1
J W D
CPU1
CPU2
JOH1
J D 1
J4
F
4
J4
F
5
PWR
Fail
S P K R
Bank1
Bank2
Bank3
Bank4
PCI-Ex8
PCI-Ex8
SATA
S I/O
Graphic
Memory
SMB
IPMB COM2
BIOS
WOR
JS10
JPS1
SATAII
JWF2
JP18
JWF1
JP17
SATA0
SATA1
Fan5
Fan4
JP10
JP11
12V
8 Pin
PWR
12V
4 Pin
PWR
J S 9
M
a
rv
e
ll
S
A
T
A
#
0
-3
J 3
J 4
Содержание Super X6DHR-TG
Страница 1: ...X6DHR TG USER S MANUAL Revision 1 0 SUPER...
Страница 9: ...Chapter 1 Introduction 1 3 Introduction Figure 1 1 X6DHR TG Image...
Страница 80: ...A 6 X6DHR TG User s Manual Notes...
Страница 86: ...B 6 X6DHR TG User s Manual Notes...