2-10
X6DHR-TG User's Manual
Power Button
Overheat LED
1
NIC1 LED
Reset Button
2
Power Fail LED
HDD LED
Power LED
Reset
Pwr
Vcc
Vcc
Vcc
Vcc
Ground
Ground
19
20
Vcc
X
Ground
NMI
X
NIC2 LED
Vcc
K B
DIMM 4B
M
o
u
s
e
U S B
0 / 1
COM1
DIMM 4A
DIMM 3B
DIMM 3A
DIMM 2B
DIMM 2A
DIMM 1B
DIMM 1A
GLAN1
GLAN2
V
G
A
Battery
JPG1
JPL1
RAGE-
X L
GLAN
C T R L
P X H
PCI-X 133 MHz
PCI-X 100 MHz
E 7 5 2 0
(North Bridge)
ICH5R
(South
Bridge)
ZCR RAID
IPMI 2.0
IDE #1
IDE #2
Floppy
WOL
COM2
Fan3
U S B 2 / 3
JBT1
F
P
C
T
R
L
FAN2
F A N 1
20-Pin ATX PW
PW SMB
J L 1
J W D
CPU1
CPU2
JOH1
J D 1
J
4
F
4
J
4
F
5
PWR
Fail
S P K R
Bank1
Bank2
Bank3
Bank4
PCI-Ex8
PCI-Ex8
S
A
T
A
S I/O
Graphic
Memory
SMB
IPMB COM2
BIOS
WOR
JS10
JPS1
SATAII
JWF2
JP18
JWF1
JP17
SATA0
SATA1
Fan5
Fan4
JP10
JP11
12V
8 Pin
PWR
12V
4 Pin
PWR
J S 9
M
a
rv
e
ll
S
A
T
A
#
0
-3
J 3
J 4
Power LED
The Power LED connection is lo-
cated on pins 15 and 16 of JF1.
Refer to the table on the right for
pin definitions.
NMI Button
The non-maskable interrupt button
header is located on pins 19 and
20 of JF1. Refer to the table on
the right for pin definitions.
Pin
Number
19
20
Definition
Control
Ground
NMI Button Pin
Definitions (JF1)
Pin
Number
15
16
Definition
Vcc
Control
PWR_LED Pin Definitions
(JF1)
NMI
PWR LED
Содержание Super X6DHR-TG
Страница 1: ...X6DHR TG USER S MANUAL Revision 1 0 SUPER...
Страница 9: ...Chapter 1 Introduction 1 3 Introduction Figure 1 1 X6DHR TG Image...
Страница 80: ...A 6 X6DHR TG User s Manual Notes...
Страница 86: ...B 6 X6DHR TG User s Manual Notes...