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SUPER P5MMA98/P5MMS98/P5MMA2/P5MMS2 User's Manual
SDRAM CAS# Latency
The settings for this option are 3 or 2. The Optimal and Fail-Safe
default settings are 2. When set to 2, a CAS# latency of 2 is used
for all SDRAM cycles. When set to 3, a CAS# latency of 3 is used for
all SDRAM cycles.
SDRAM RAS# Timing
This controls the RAS# active to precharge time. The settings for
this option are 5 or 4. The Optimal and Fail-Safe default settings
are 5.
SDRAM Speculative Read Logic
The settings for this option are Enabled or Disabled. Set this to
Enabled to allow the system to perform SDRAM read cycle base on
the expected logic specified by the chipset. The Optimal and Fail-
Safe default settings are Disabled.
DRAM Speed
This option should be set according to the speed of the DRAM in
the system. The value of this option determines how the DRAM
timings should be programmed in the chipset. The settings for this
option are Manual, 60ns or 70ns. The Optimal and Fail-Safe default
settings are Manual.
DRAM Read Burst Timing
You can define the DRAM read burst timing by setting the DRAM
speed to Manual. This option sets the timing for system memory
burst mode read operations. The settings for this option are
x4EDO/x4FPM, x3EDO/x4FPM, or x2EDO/x3FPM. The Optimal and
Fail-Safe default settings are x4EDO/x4FPM.
