Supermicro B2SD1-8C-TF, Руководство пользователя

Страница: 56 / 98

Super B2SD2(1)-8C/12C/16C-TF MicroBlade Module User's Manual
56
SDDC
Single device data corr1 (SDDC Plus One) organizes data in a single bundle
(x4/x8 DRAM). If any or all of the bits become corrupted, corrections occur. The x4
condition is corrected on all cases. The x8 condition is corrected only if the system is
in Lockstep Mode. The options are
Disable and Enable.
ADDDC Sparing
Adaptive Double Device Data Correction (ADDDC) Sparing detects when the prede-
termined threshold for correctable errors is reached, copying the contents of the failing
DIMM to spare memory. The failing DIMM or memory rank will then be disabled. The
options are
Disable
and Enable.
Patrol Scrub
Patrol Scrub is a process that allows the CPU to correct correctable memory errors
detected on a memory module and send the correction to the requestor (the original
source). When this feature is set to Enable, the IO hub will read and write back one
cache line every 16K cycles if there is no delay caused by internal processing. By us-
ing this method, roughly 64 GB of memory behind the IO hub will be scrubbed every
day. The options are Disable and Enable .
*If the feature above is set to Enable, Patrol Scrub Interval will be available for
configuration:
Patrol Scrub Interval
This feature allows you to decide how many hours the system should wait before the
next complete patrol scrub is performed. Use the keyboard to enter a value from 0-24.
The default setting is
24 .

IIO Configuration
EV DFX Features
When this feature is set to Enable, the EV_DFX Lock Bits that are located on a proces-
sor will always remain clear during electric tuning. The options are
Disable
and Enable.

CPU Configuration
IOU0 (II0 PCIe Br1)
Use this feature to configure the PCI-E port Bifuraction setting for a PCI-E port speci -
fied by the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto .