Supermicro AS-1010P-8, Руководство пользователя

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Chapter 7: BIOS
7-9
ECC Confi guration
DRAM ECC Enable
DRAM ECC allows hardware to report and correct memory errors automati-
cally. Options are Enabled and Disabled.
MCA DRAM ECC Logging
When "Enabled", MCA DRAM ECC logging and reporting is enabled.
Options are Enabled and Disabled .
ECC Chip Kill
Allows the user to Enable or Disable ECC Chip Kill.
DRAM Scrub Redirect
Allows system to correct DRAM ECC errors immediately, even with
background scrubbing on. Options are Enabled and Disabled .
DRAM BG Scrub
Corrects memory errors so later reads are correct. Options are Dis-
abled and various times in nanoseconds and microseconds.
L2 Cache BG Scrub
Allows L2 cache RAM to be corrected when idle. Options are Disabled and
various times in nanoseconds and microseconds.
Data Cache BG Scrub
Allows L1 cache RAM to be corrected when idle. Options are Disabled and
various times in nanoseconds and microseconds.
Power Down Control
This feature allows DIMMs to enter a power down mode by deasserting the clock
enable signal when DIMMs are not in use. The options are Auto and Disabled.
Memory Timing Parameters
Select CPU Node0 or CPU Node1 to view the parameters for that node in the
fi eld below.