Chapter 2: Installation
2-29
FAN2
JP9
SW1
T-SGPIO1
JSTBY1
JIPMB1
JPW2
JSD1
LED3
LED2
JD1
LED5
LED1
JPI2C1
BT1
JPW1
JTPM1
FANA FAN3
FAN1
FAN2
FAN4
JPL1
JPL2
JPME2
JWD1
JPG1
JBR1
JPME1
J19 J18
J7
JVR1
JI2C1
JI2C2
JOH1
JP8
JL1
JP2
JP1
JP7
USB 3.0-0
USB 3.0-1
USB 3.0-2/3
VGA
LAN2
LAN1
USB4/5
USB6/7
IPMI_LAN
COM2
COM1
P1-DIMMB1
P1-DIMMB2
P1-DIMMA2
P1-DIMMA1
PCH SLOT4 PCI-E 2.0 X4(IN X8)
CPU SLOT5 PCI-E 3.0 X8
CPU SLOT6 PCI-E 3.0 X8(IN X16)
JF1
I-SATA4
I-SATA3
I-SATA5
I-SATA2
I-SATA1
I-SATA0
USB8/9
JRK1
T-SGPIO2
JPB1
X10SLM-F/X10SLL(-F/SF/S)
Rev. 1.02
BMC FW
FP Control
PCH
BMC
CTRL
CPU
SP1
LED4
IPMI Code
BAR Code
MAC Code
JBT1
BIOS
C
A.T-SGPIO 1
B.T-SGPIO 2
C.JTPM1
A
B
T-SGPIO 1/2 Headers
Two Serial-Link General Purpose
Input/Output headers (T-SGPIO 1/2)
are located on the motherboard to en-
hance system performance. See the
table on the right for pin definitions.
Note:
NC= No Connection
T-SGPIO
Pin Definitions
Pin# Definition
Pin Definition
1
NC
2
NC
3
Ground
4
Data
5
Load
6
Ground
7
Clock
8
NC
TPM Header/Port 80 Header
A Trusted Platform Module/Port 80
header is located at JTPM1 to provide
TPM support and Port 80 connection.
Use this header to enhance system
performance and data security. See
the table on the right for pin defini
-
tions.
TPM/Port 80 Header
Pin Definitions
Pin # Definition
Pin # Definition
1
LCLK
2
GND
3
LFRAME#
4
<(KEY)>
5
LRESET#
6
+5V
7
LAD 3
8
LAD 2
9
+3.3V
10
LAD1
11
LAD0
12
GND
13
SMB_CLK
14
SMB_DAT
15
+3V Stby
16
SERIRQ
17
GND
18
CLKRUN#
19
LPCPD#
20
LDRQ#