
Smart Machine Smart Decision
SIM5800_Hardware Design_V1.01
12
2018-10-08
3.
Pin definitions
3.1
Pin Assignment
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
110
109
108
107
106
105
104
103
102
101
100
11
1
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
11
5
11
4
11
3
11
2
13
0
12
9
12
8
12
7
12
6
12
5
12
4
12
3
12
2
12
1
12
0
11
9
11
8
11
7
11
6
14
6
14
5
14
4
14
3
14
2
14
1
14
0
13
9
13
8
13
7
13
6
13
5
13
4
13
3
13
2
13
1
VBAT
VBAT
GND
MIC1P
MIC1N
EAR_MICP
GND_EARMICN
REC_P
REC_N
SPK_P
SPK_N
GND
USB_DM
USB_DP
GND
USB_ID
USIM2_DET
USIM2_RST
USIM2_CLK
USIM2_DATA
USIM2_VDD
USIM1_DET
USIM1_RST
USIM1_CLK
USIM1_DATA
USIM1_VDD
GND
VIB_DRV_P
PWM
CTP_EINT
CTP_RST
VMC_PMU
GND
UART1_TXD
UART1_RXD
UART1_CTS
UART1_RTS
SIM5800
147
148
149
150
151
152
153
154
179
180
181
182
195
196
197
198
163
164
165
166
167
168
169
170
187
188
189
190
203
204
205
206
171
172
173
174
175
176
177
178
191
192
193
194
207
208
209
210
155
156
157
158
159
160
161
162
183
184
185
186
199
200
201
202
RESET
MIC_BIAS1
MIC_BIAS0
VCAMA_PMU
VCAMD_IO_PMU
VCAMD_PMU
VCAM_AF_PMU
RESERVED
RESERVED
MIC2P
MIC2N
POWER
AUDIO
GND
UIM
LCM+CTP
SD
CAMERA
ANT
NC
NC
GPIO81
GPIO82
GPIO83
GPIO84
GND
ISINK0
ISINK1
ISINK2
ISINK3
GPIO21
GPIO20
GPIO19
GPIO18
GPIO65
GND
GPIO12
GPIO11
SENSOR_I2C_SDA
SENSOR_I2C_SCL
GPIO69
GND
GND
ANT_MAIN
GND
GND
CAM_I2C_SDA
CAM_I2C_SCL
CAM1_PWDN
CAM1_RST
CAM0_PWDN
CAM0_RST
GND
ANT_WIFI/BT
GND
CAM1_MCLK
CAM0_MCLK
V
M
C
H
_P
M
U
S
D
_C
LK
S
D
_C
M
D
S
D
_D
A
T
A
0
S
D
_D
A
T
A
1
S
D
_D
A
T
A
2
S
D
_D
A
T
A
3
S
D
_D
E
T
U
S
B
_B
O
O
T
C
T
P
_I
2C
_S
C
L
C
T
P
_I
2C
_S
D
A
LC
D
_R
S
T
LC
D
_T
E
G
N
D
M
IP
I_
D
S
I_
C
LK
N
M
IP
I_
D
S
I_
C
LK
P
M
IP
I_
D
S
I_
L0
N
M
IP
I_
D
S
I_
L0
P
M
IP
I_
D
S
I_
L1
N
M
IP
I_
D
S
I_
L1
P
M
IP
I_
D
S
I_
L2
N
M
IP
I_
D
S
I_
L2
P
N
C
N
C
G
N
D
M
IP
I_
C
S
I0
_C
LK
N
M
IP
I_
C
S
I0
_C
LK
P
M
IP
I_
C
S
I0
_L
0N
M
IP
I_
C
S
I0
_L
0P
M
IP
I_
C
S
I0
_L
1N
M
IP
I_
C
S
I0
_L
1P
G
N
D
M
IP
I_
C
S
I1
_C
LK
N
M
IP
I_
C
S
I1
_C
LK
P
M
IP
I_
C
S
I1
_L
0N
M
IP
I_
C
S
I1
_L
0P
UART2_RXD
UART2_TXD
V
B
A
T
V
B
A
T
G
N
D
G
N
D
V
B
U
S
V
B
U
S
G
N
D
H
S
_D
E
T
H
P
H
_L
G
N
D
H
P
H
_R
G
N
D
B
A
T
_I
D
N
C
G
N
D
N
C
G
N
D
V
IO
28
_P
M
U
A
D
C
N
C
V
R
T
C
V
IO
18
_P
M
U
N
C
N
C
G
N
D
A
N
T
_G
N
S
S
G
N
D
G
P
IO
2_
S
P
IM
O
S
I
G
P
IO
3_
S
P
IM
IS
O
G
P
IO
0_
S
P
IC
S
G
P
IO
1_
S
P
IS
C
K
N
C
P
W
R
K
E
Y
V
G
P
3_
P
M
U
V
G
P
2_
P
M
U
N
C
Figure 2: Module pin diagram (Top view)